Abstract: Disclosed is a container capacitor structure and method of constructing it. An etch mask and etch are used to expose portions of an exterior surface of electrode (“bottom electrodes”) of the container capacitor structure. The etch provides a recess between proximal pairs of container capacitor structures, which recess is available for forming additional capacitance. Accordingly, a capacitor dielectric and a top electrode are formed on and adjacent to, respectively, both an interior surface and portions of the exterior surface of the first electrode. Advantageously, surface area common to both the first electrode and second electrodes is increased over using only the interior surface, which provides additional capacitance without a decrease in spacing for clearing portions of the capacitor dielectric and the second electrode away from a contact hole location.

Abstract: A small size electronic component has a small direct current resistance value of a conductor pattern and minimal dimensional irregularity of a conductor pattern. In order to form such a component, a photosensitive conductive paste applied on a ceramic substrate and is then exposed through a photo mask and developed so as to form a lower conductor pattern layer of a coil conductor pattern. Then an insulating paste is applied on the ceramic substrate so as to cover the lower conductor pattern layer and the insulating paste is removed with a solvent until at least the upper surface of the lower conductor pattern layer is exposed so as to form an inter-line insulating layer. Furthermore, after applying a photosensitive conductive paste as a film, the exposure and development operation is conducted again while using the photo mask so as to form an upper conductor pattern layer on the lower conductor pattern layer.

Abstract: The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the same. In one aspect, the present invention provides a semiconductor device having a dielectric layer located over a conductive feature and a conductive via located within the dielectric layer and contacting the conductive feature. The semiconductor device, among other elements, may further include a dummy conductive via located proximate the conductive via and contacting the conductive feature. One of the intents of the dummy conductive via is to attempt to trap vacancies associated with the conductive feature or the conductive via.

Abstract: Undesirable transistor leakage in transistor structures becomes greatly reduced in substrates having a doped implant region formed via pulling back first and second layers of a process stack. A portion of the substrate, which also has first and second layers deposited thereon, defines the process stack. The dopant is selected having the same n- or p-typing as the substrate. Through etching, the first and second layers of the process stack become pulled back from a trench wall of the substrate to form the implant region. Occupation of the implant region by the dopant prevents undesirable transistor leakage because the electrical characteristics of the implant region are so significantly changed, in comparison to central areas of the substrate underneath the first layer, that the threshold voltage of the implant region is raised to be about equivalent to or greater than the substantially uniform threshold voltage in the central area.

Abstract: A method of forming a memory array includes forming a stack of two or more layers of memory material on a substrate, each layer of memory material having an array of memory cells, and forming one or more contacts that pass through each of the layers of memory material.

Abstract: A semiconductor device comprising: a first insulation film 60 formed above a base substrate 10; a second insulation film 61 formed on the first insulation film and having different etching characteristics from the first insulation film; and a capacitor 79 including a storage electrode 68 formed on the second insulation film, projected therefrom, the storage electrode being formed, extended downward from side surfaces of the second insulation film. The lower ends of the storage electrodes are formed partially below the etching stopper film, whereby the storage electrodes are fixed by the etching stopper film. Accordingly, the storage electrodes are prevented from peeling off in processing, such as wet etching, etc. The semiconductor device can be fabricated at high yields.

Abstract: A semiconductor device capable of effectively eliminating noise on multilayered power lines with a bypass capacitor. A first power line is connected to the bypass capacitor. A second power line is a line from which a part located above the bypass capacitor is removed. Contacts connect the first and second power lines. Therefore, noise appearing on the second power line travels to the first power line, resulting in effectively eliminating the noise with the bypass capacitor.

Abstract: A semiconductor device includes a semiconductor substrate. A gate electrode is formed on the semiconductor substrate via a gate insulating film. A source region and a drain region of a first conductivity type are formed on the first side and the second side of the gate electrode, respectively, in the semiconductor substrate. A punch-through stopper region of a second conductivity type is formed in the semiconductor substrate such that the second conductivity type punch-through stopper region is located between the source region and the drain region at distances from the source region and the drain region and extends in the direction perpendicular to the principal surface of the semiconductor substrate. The concentration of an impurity element of the second conductivity type in the punch-through stopper region is set to be at least five times the substrate impurity concentration between the source region and the drain region.

Abstract: The present invention has an object to provide a semiconductor device that is equipped with a high breakdown voltage transistor of a high junction breakdown voltage characteristic and a low voltage transistor of a high electric current drive characteristic to thereby ensure the element isolation performance in the both transistor forming regions. The semiconductor device is equipped with a high breakdown voltage transistor (a) and low voltage transistor (b) the widths of whose side walls are different from each other. The side walls of the high breakdown voltage transistor (a) each consist of four layers of first side wall film, second side wall film, third side wall film, and fourth side wall film that are formed in such a way that they are laminated from both side surfaces of a gate electrode in directions that are sidewardly remote away from this gate electrode.

Abstract: An aspect of the present invention includes a first conductive type semiconductor region formed in a semiconductor substrate, a gate electrode formed on the first conductive type semiconductor region, a channel region formed immediately below the gate electrode in the first conductive type semiconductor region, and a second conductive type first diffusion layers constituting source/drain regions formed at opposite sides of the channel region in the first conductive type semiconductor region, the gate electrode being formed of polycrystalline silicon-germanium, in which the germanium concentration of at least one of the source side and the drain side is higher than that of the central portion.

Abstract: A leadframe for use with integrated circuit chips comprising a plated layer of gold selectively covering areas of said leadframe intended for solder attachment; and said gold layer providing a visual distinction to said areas.

Abstract: A multi-chip package includes first through Nth semiconductor chips, each of which includes an input/output pad, an input/output driver coupled to the input/output pad, and an internal circuit. Each of the first through Nth semiconductor chips includes an internal pad for coupling the internal input/output driver and the internal circuit. The internal pads of the first through Nth semiconductor chips are coupled to each other such as via a common pad installed at a substrate. The input/output pad of the first semiconductor chip directly receives an input/output signal from a corresponding pin of the multi-chip package. The second through Nth semiconductor chips indirectly receive the input/output signal via the internal pads coupled to each other.

Abstract: The planes of chips in a flip-chip arrangement, when at least one of the chips has an insulating layer running through it, may be electrically connected together by incorporating into the top chip a flexible metalized structure which is pinned to the top layer of the bottom chip using a wire bond ball which is connected to a wire that is attached to a pad on the top layer of the upper chip. A single connection connects both layers of the top chip to the layer on the bottom chip. The flexible structure may be similar to a collapsible cup with a hole in the middle or it may be a tiltable micro mirror.

Abstract: In a semiconductor storage device, a gate insulating film and a gate electrode are laid on a first conductivity type semiconductor substrate, and charge holding portions are formed on both sides of the gate electrode. Second conductivity type first and second diffusion layer regions are formed in regions of the semiconductor substrate corresponding to the charge holding portions. The charge holding portions are each structured so as to change, in accordance with an electric charge amount held in the charge holding portions, a current amount flowing from one of the second conductivity type diffusion layer regions to the other of the diffusion layer regions through a channel region when voltage is applied to the gate electrode. Part of each charge holding portion is present below an interface of the gate insulating film and the channel region.

Abstract: A field effect transistor comprises, at least, a channel forming region formed in a semiconductor layer, and a gate electrode provided in face-to-face relation with the channel forming region via a gate insulating film, wherein the semiconductor layer is made of a mixture of a semiconductor material layer and conductive particles. The field effect transistor is capable of enhancing a carrier mobility.

Abstract: An SCR device having a first P type region disposed in a semiconductor body and electrically connected to anode terminal of the device. At least one N type region is also disposed in the body adjacent the first P type region so as to form a PN junction having a width Wn near a surface of the semiconductor body. A further P type region is also disposed in the body to form a further PN junction with the N type region, with the junction having a width Wp near the body surface, with Wp being at least 1.5 times width Wn. A further N type region is provided which is electrically connected to a cathode terminal of the device and forming a third PN junction with the further N type region.

Abstract: This invention provides a solution to increase the yield strength and fatigue strength of miniaturized springs, which can be fabricated in arrays with ultra-small pitches. It also discloses a solution to minimize adhesion of the contact pad materials to the spring tips upon repeated contacts without affecting the reliability of the miniaturized springs. In addition, the invention also presents a method to fabricate the springs that allow passage of relatively higher current without significantly degrading their lifetime.

Abstract: A method for minimizing slip line faults on a surface of a semiconductor wafer that has been obtained using a transfer technique. The method includes heating the semiconductor wafer from an ambient temperature to a first higher temperature and pausing the heating at the first higher temperature for a time sufficient to stabilize the wafer. Then the wafer is heated further from the first higher temperature to a target higher temperature during a predetermined time interval. The further heating during an initial portion of the time interval is conducted at a relatively low heating rate and the heating during a final portion of the time interval is conducted at a relatively higher heating rate to thus minimize slip line faults in the surface of the wafer.

Abstract: A semiconductor device is manufactured by forming a first insulating layer on a semiconductor substrate. First contact pads and second contact pads are formed that penetrate through the first insulating layer and are electrically connected to the semiconductor substrate. A second insulating layer is formed that has guide contact holes that expose upper surfaces of the first contact pads. An etch stopper is formed on bottoms and sidewalls of the guide contact holes of the second insulating layer. Bit lines are formed that are electrically connected to the semiconductor substrate by the second contact pads. The bit lines are electrically isolated from the first contact pads.

Abstract: The semiconductor device comprises a gate interconnection 24a including a gate electrode formed over a semiconductor substrate 14 with a gate insulation film 22 formed therebetween; a first source/drain diffused layer 28 formed near the end of the gate interconnection 24a; a second source/drain diffused layer 34 formed remote from the gate interconnection 24a and the first source/drain diffused layer 28; and an insulation film 40 formed over the gate interconnection 24a, the first source/drain diffused layer 28 and the second source/drain diffused layer 34, and having a groove-shaped opening 42a formed in, which integrally exposes the gate interconnection 24a, one of the first source/drain diffused layer 28, and one of the second source/drain diffused layer 34; and a contact layer 48a buried in the groove-shaped opening 42a. The groove-shaped openings 42a for the contact layers 48a to be buried in can be formed without failure.