Abstract: Methods, systems, and devices for a memory device with a high resistivity thermal barrier are described. In some examples a barrier material may be positioned over a memory cell region, an oxide region, and/or a through-silicon via (TSV). The barrier may include a first region above the memory cell region and a second region above the TSV. A process, such as a plasma treatment, may be applied to the barrier, which may result in the first and second regions having different thermal resistivities (e.g., different densities). Accordingly, due to the different thermal resistivities, the memory cells may be thermally insulated from thermal energy generated in the memory device.

Abstract: A mixed semiconductor-superconductor platform is fabricated in phases. In a masking phase, a dielectric mask is formed on a substrate, such that the dielectric mask leaves one or more regions of the substrate exposed. In a selective area growth phase, a semiconductor material is selectively grown on the substrate in the one or more exposed regions. In a superconductor growth phase, a layer of superconducting material is formed, at least part of which is in direct contact with the selectively grown semiconductor material. The mixed semiconductor-superconductor platform comprises the selectively grown semiconductor material and the superconducting material in direct contact with the selectively grown semiconductor material.

Abstract: Provided is a display device. The display device includes: one or more pixels placed in an active area and a pixel circuit associated with the pixels; and a power supply line placed in an inactive area outside the active area and connected to the pixel circuit. At least one side of the power supply line may be covered with an overcoating layer. The overcoating layer includes a first portion adjacent to the side of the power supply line and a second portion which is farther from the power supply line than the first portion. The first portion has a smaller thickness than the second portion. The first portion may be about half the thickness of the second portion.

Abstract: An array substrate, a display panel and a manufacturing method thereof are provided. The array substrate includes a base substrate including a peripheral region; and a lead region located in the peripheral region, the lead region including a plurality of leads, wherein a main plane of the base substrate provided with the plurality of leads includes a first side edge, and the plurality of leads extend to the first side edge, a lateral surface of the base substrate at the first side edge is provided with a concave portion, and an electrode electrically connected with the plurality of leads is disposed in the concave portion.

Abstract: A method of fabricating a device including a superconductive layer includes depositing a seed layer on a substrate, exposing the seed layer to an oxygen-containing gas or plasma to form a modified seed layer, and after exposing the seed layer to the oxygen-containing gas or plasma depositing a metal nitride superconductive layer directly on the modified seed layer. The seed layer is a nitride of a first metal, and the superconductive layer is a nitride of a different second metal.

Abstract: A carrier substrate is configured to carry at least one electronic chip and includes a mounting front face. An encapsulating cover is mounted on the front face of the carrier substrate through a mounting. This mounting includes at least one seating surface through which the cover and the carrier substrate make contact. At least one adhesive bead is located elsewhere than the seating surface in order to securely fasten the encapsulation cover and the carrier substrate.

Abstract: To provide a light-emitting device in which variation in luminance among pixels caused by variation in threshold voltage of transistors can be suppressed. The light-emitting device includes a transistor including a first gate and a second gate overlapping with each other with a semiconductor film therebetween, a first capacitor maintaining a potential difference between one of a source and a drain of the transistor and the first gate, a second capacitor maintaining a potential difference between one of the source and the drain of the transistor and the second gate, a switch controlling conduction between the second gate of the transistor and a wiring, and a light-emitting element to which drain current of the transistor is supplied.

Abstract: According to an exemplary embodiment of the present invention, provided is a method for manufacturing a superconductor including magnesium diboride, the method including: a first mixture preparation step of preparing a first mixture including a boron powder and a liquid chlorinated hydrocarbon compound; a second mixture preparation step of preparing a second mixture including the first mixture and a magnesium powder; a molded body manufacturing step of manufacturing a molded body by pressurizing the second mixture; and a sintering step of sintering the molded body to manufacture a superconductor including magnesium diboride.

Abstract: A semiconductor device including a substrate having a plurality of active fins, each of the plurality of active fins extending in a first direction, first and second gate structures crossing over the plurality of active fins, the first and second gate structures extending in a second direction different from the first direction, the first and second gate structures spaced apart from each other in the first direction, at least one insulating barrier extending in the first direction and between the plurality of active fins, the insulating barrier separating lower portions of the first and second gate structures from each other, and a gate isolation layer connected to a portion of the insulating barrier, the gate isolation unit separating upper portions of the first and second gate structures from each other may be provided.

Abstract: A hearing assistance device to provide sound to the ear of a user, the device comprising a housing, hearing assistance electronics enclosed in the housing, an acoustic transducer adapted to be worn in the ear, a cable assembly adapted to connect the acoustic transducer to the hearing assistance electronics, a wireless communications receiver connected to the hearing assistance electronics, and an antenna comprising one or more conductors forming at least a portion of the cable assembly.

Abstract: A light detecting device includes a light absorbing layer configured to absorb light in a wavelength range from visible light to short-wave infrared (SWIR); a first semiconductor layer provided on a first surface of the light absorbing layer; an anti-reflective layer provided on the first semiconductor layer and comprising a material having etch selectivity with respect to the first semiconductor layer; and a second semiconductor layer provided on a second surface of the light absorbing layer. The first semiconductor layer has a thickness less than 500 nm so as to be configured to allow light to transmit therethrough in the wavelength range from visible light to SWIR.

Abstract: Techniques for enhancing the absorption of photons in semiconductors with the use of microstructures are described. The microstructures, such as pillars and/or holes, effectively increase the effective absorption length resulting in a greater absorption of the photons. Using microstructures for absorption enhancement for silicon photodiodes and silicon avalanche photodiodes can result in bandwidths in excess of 10 Gb/s at photons with wavelengths of 850 nm, and with quantum efficiencies of approximately 90% or more.

Abstract: A dark reference device comprises: a photodiode comprising an optical active area; a light shield configured to prevent light from entering said optical active area, wherein said light shield comprises first and second overlapping metal covers, and wherein each of said metal covers comprises a plurality of openings overlapping said optical active area.

Abstract: A phototransistor device to act as an artificial photonic synapse includes a substrate and a graphene source-drain channel patterned on the substrate. A perovskite quantum dot layer is formed on the graphene source-drain channel. The perovskite quantum dot layer is methylammonium lead bromide material. A method of operating the phototransistor device as an artificial photonic synapse includes applying a first fixed voltage to a gate of the phototransistor and a second fixed voltage across the graphene source-drain channel. A presynaptic signal is applied as stimuli across the graphene source-drain channel. The presynaptic signal includes one or more pulses of light or electrical voltage. A current across the graphene source-drain channel is measured to represent a postsynaptic signal.

Abstract: The invention relates to a method for fabricating a thermal detector (1), comprising the following steps: forming a first stack (10), comprising a thermal detector (20), a mineral sacrificial layer (15) and a thin encapsulation layer (16) having a lateral vent (17.1); forming a second stack (30), comprising a thin sealing layer (33) and a getter portion (34); eliminating the mineral sacrificial layer (15); assembling by direct bonding the thin sealing layer (33), brought into contact with the thin encapsulation layer (16) and blocking the lateral vent (17.1), the getter portion (34) being located in the lateral vent (17.1).

Abstract: An atomic orbital based memory storage is provided that includes a plurality of surface atoms forming dangling bonds (DBs) and a subset of the plurality of surface atoms passivated with spatial control to form covalent bonds with hydrogen, deuterium, or a combination thereof. The atomic orbital based data storage that can be rewritten and corrected as needed. The resulting data storage is also archival and capable of high data densities than any known storage as the data is retained in a binary storage or a given orbital being passivated or a dangling bond (DB). A method of forming and reading the atomic orbital data storage is also provided. The method including selectively removing covalent bonds to form dangling bonds (DBs) extending from a surface atom by hydrogen lithography and imaging the covalent bonds spatially to read the atomic orbital data storage.

Abstract: A display substrate and a manufacturing method thereof, and a display panel are provided. The display substrate includes a base substrate having a display region and a peripheral region adjacent to the display region, the peripheral region being provided therein with a gate driver-on-array circuit including a plurality of transistors and capacitors, all of the transistors are provided in a transistor region, at least a part of the plurality of capacitors are provided in a capacitor region, and the capacitor region is located on a side of the transistor region distal to the display region; and an encapsulation structure for encapsulating the display region and the transistor region together; the peripheral region further including a sealing region for arranging a sealing structure therein, the capacitor region is located in the sealing region, and the sealing region is provided on a side of the encapsulation structure distal to the display region.

Abstract: At least one doped silicon region is formed in a silicon layer of a semiconductor substrate, and a silicon oxide layer is formed over the silicon layer. A germanium-containing material portion is formed in the semiconductor substrate to provide a p-n junction or a p-i-n junction including the germanium-containing material portion and one of the at least one doped silicon region. A capping material layer that is free of germanium is formed over the germanium-containing material portion. A first dielectric material layer is formed over the silicon oxide layer and the capping material layer. The first dielectric material layer includes a mesa region that is raised from the germanium-containing material portion by a thickness of the capping material layer. The capping material layer may be a silicon capping layer, or may be subsequently removed to form a cavity. Dark current is reduced for the germanium-containing material portion.

Abstract: In a semiconductor process, a seamless tungsten plug is formed in an inter-layer dielectric by forming the inter-layer dielectric from multiple oxide layers having different wet etch rates, from lowest wet-etch rate for the lowest layer to highest wet-etch rate for the highest layer, forming a hole or trench in the inter-layer dielectric using a dry etch process, reconfiguring the hole or trench to have sloped side walls by performing a wet etch step, and filling the hole or trench with tungsten and etching back the tungsten to form a seamless tungsten plug.

Abstract: Embodiments of the invention are directed to a fabrication method that includes forming a first-region channel over a first region of a substrate, wherein the first-region channel further includes lateral sidewalls having a length (L), a first end sidewall having a first width (W1), and a second end sidewall having a second width (W2). L is greater than W1, and L is greater than W2. A first stress anchor is formed on the first end sidewall of the first-region channel, and a second stress anchor is formed on the second end sidewall of the first-region channel. The first stress anchor is configured to impart strain through the first end sidewalls to the first-region channel. The second stress anchor is configured to impart strain through the second end sidewalls to the first-region channel.