Abstract: The present disclosure relates to a method for manufacturing a monolithic tandem solar cell in which a perovskite solar cell is laminated and bonded on a silicon solar cell. According to the present disclosure, a first microporous precursor thin film is formed through a sputtering method on a substrate having an unevenly structured texture and then a halide thin film is formed on the first microporous precursor thin film to form a perovskite absorption layer, whereby light reflectance can be reduced and a path of light can be increased, and accordingly a light absorption rate can be increased.

Abstract: A semiconductor device includes a substrate, first and second source/drain features, and a dielectric plug. The substrate has a semiconductor fin. The first and second source/drain features are over first and second portions of the semiconductor fin, respectively. The dielectric plug is at least partially embedded in a third portion of the semiconductor fin. The third portion is in between the first and second portions of the semiconductor fin. The dielectric plug includes a first dielectric material and a second dielectric material different from the first dielectric material.

Abstract: The present invention relates to semiconductor devices, such as microelectromechanical (MEMS) devices, with improved resilience during manufacturing. In one embodiment, a MEMS device includes a MEMS structure; a substrate situated parallel to the MEMS structure and positioned a first distance from the MEMS structure; and a bump stop structure formed on the substrate between the substrate and the MEMS structure, wherein the bump stop structure substantially traces a perimeter of the substrate, wherein the bump stop structure extends from the substrate to a second distance from the MEMS structure, and wherein the second distance is greater than zero and less than the first distance.

Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a substrate, a dielectric layer disposed on the substrate, bit lines disposed on the dielectric layer, spacers and a contact. The substrate has active areas arranged in parallel with each other. The bit lines are arranged in parallel with each other. Each bit line is partially overlapped with the corresponding active area. Each bit line has first portions and second portions arranged alternately in an extending direction thereof, and a width of the first portions is smaller than that of the second portions. The spacers are disposed on the sidewalls of each bit line. The contact is disposed between the adjacent bit lines and adjacent to the corresponding first portion of at least one of the adjacent bit lines, penetrates through the dielectric layer, and is in contact with the corresponding active area.

Abstract: A photomemcapacitor device comprising a metal oxide semiconductor material is provided. The photocapacitor device comprises a p-n junction and a Schottky junction. A photomemcapacitor is provided for responding to photons at specified wavelengths.

Abstract: Embodiments of the invention are directed to a resistive switching device (RSD). A non-limiting example of the RSD includes a fin-shaped element formed on a substrate, wherein the fin-shaped element includes a source region, a central channel region, and a drain region. A gate is formed over a top surface and sidewalls of the central channel region. The fin-shaped element is doped with impurities that generate interstitial charged particles configured to move interstitially through a lattice structure of the fin-shaped element under the influence of an electric field applied to the RSD.

Abstract: An embodiment is a package including a first package structure. The first package structure includes a first integrated circuit die having an active side and a back-side, the active side comprising die connectors, a first electrical connector adjacent the first integrated circuit die, an encapsulant laterally encapsulating the first integrated circuit die and the first electrical connector, a first redistribution structure on and electrically connected to the die connectors of the first integrated circuit die and the first electrical connector, and thermal elements on the back-side of the first integrated circuit die. The package further includes a second package structure bonded to the first electrical connector and the thermal elements with a first set of conductive connectors.

Abstract: A method of forming an interconnect structure for an integrated circuit device is provided. The method includes forming a conductive line layer over a semiconductor substrate. The conductive line layer includes a metal line. The method also includes forming a conductive pillar on and in contact with the metal line. The method further includes depositing a dielectric layer over the conductive line layer to cover the conductive pillar, and etching the dielectric layer to form a trench. The conductive pillar is exposed through the trench. In addition, the method includes filling the trench with a conductive material to form a conductive line.

Abstract: A method of fabricating the vertical field effect transistor includes forming a dielectric layer on a metal semiconductor alloy layer that is present on a substrate of a semiconductor material. The dielectric layer is bonded to a supporting substrate. The substrate of the semiconductor material is cleaved, wherein a remaining portion of the semiconductor material provides a semiconductor surface layer in direct contact with the metal semiconductor alloy layer. A vertical fin type field effect transistor (FinFET) is formed atop the stack of the semiconductor surface layer, the metal semiconductor alloy layer, the dielectric layer and the supporting substrate, wherein the semiconductor surface layer provides at least one of a source region or a drain region of the FinFET and the metal semiconductor alloy provides a contact to the source region or the drain region of the FinFET.

Abstract: The light receiving element unit includes a first light receiving element having a light receiving region on the main surface side of the first semiconductor substrate and a second light receiving element having a light receiving region on the main surface side of the second semiconductor substrate, and a support substrate having wiring for electrically connecting the first light receiving element and the second light receiving element to the outside, one of the first light receiving element and the second light receiving element has a recess formed in a concave shape from the back surface opposite to the light receiving region toward the light receiving region, and the other is accommodated in the recess.

Abstract: A vertical field effect transistor (FET) includes a vertical semiconductor channel having a first end that contacts an upper surface of a substrate and an opposing second end that contacts a source/drain region. An electrically conductive gate encapsulates the vertical semiconductor channel. The vertical FET further includes a split-channel antifuse device between the source/drain region and the electrically conductive gate. The split-channel antifuse device includes a gate dielectric having a thickness that varies between the source/drain region and the electrically conductive gate.

Abstract: The present disclosure, in some embodiments, relates to a method of forming a package. The method includes coupling a first package component to a second package component using a first set of conductive elements. A first polymer-comprising material is formed over the second package component and surrounding the first set of conductive elements. The first polymer-comprising material is cured to solidify the first polymer-comprising material. A part of the first polymer-comprising material is removed to expose an upper surface of the second package component. The second package component is coupled to a third package component using a second set of conductive elements that are formed onto the upper surface of the second package component.

Abstract: A light emitting device according to one aspect includes a resin package and a light emitting element. The resin package includes a molded resin part defining a part of a recessed portion, and a pair of leads. The leads are exposed from the molded resin part at a bottom surface of the recessed portion. Each of the leads includes a plating layer and exposed from the molded resin part at a lower surface of the resin package. A height of a first part of the plating layer exposed from the lower surface of the resin package and adjacent to an edge of a corresponding one of the leads is different from a height of a second part of the plating layer exposed from the lower surface of the resin package. The light emitting element is mounted on the bottom surface of the recessed portion.

Abstract: Provided is a three-dimensional memory device including a substrate, first and second stacked structures and an etching stop layer. The substrate has a cell region and a periphery region. The first stacked structure is disposed on the cell region and the periphery region, and has a first vertical channel pillar on the cell region that penetrates through the first stacked structure. The second stacked structure is located on the first stacked structure, is disposed on the cell region and the periphery region, and has a second vertical channel pillar on the cell region that penetrates through the second stacked structure. The second vertical channel pillar is electrically connected to the first vertical channel pillar. The etching stop layer is located between the first and second stacked structures, is disposed on the cell region and extends onto the periphery region, and surrounds the lower portion of the second vertical channel pillar.

Abstract: A display device includes a display module and an anti-reflection member. The display module includes a display panel having a light emitting element and a sensing layer disposed on the display panel to sense touch. The anti-reflection member is disposed on the display module to reduce reflectance of light that is incident from the outside. One side of the display module has a first shape that gradually decreases in thickness outward, and one side of the anti-reflection member, which corresponds to the one side of the display module, has a second shape that gradually decreases in thickness outward.

Abstract: The present disclosure relates to a semiconductor device having a lateral resonance structure to coherently reflect light toward the image sensor. The semiconductor device includes an image sensing element arranged within a substrate. A radiation absorption region is arranged within the substrate and above the image sensor, and contains an array of protrusions having a characteristic dimension and an outer border. A resonant structure containing a plurality of deep trench isolation (DTI) structures is disposed on opposing sides of the image sensing element. The (DTI) structures surround the outer border of the array of protrusions. An inner surface of the DTI structure is laterally spaced apart from the outer border of the array of protrusions by a reflective length based on the characteristic dimension of the array of protrusions, thus affecting coherent reflection of light back toward the image sensor.

Abstract: A heterojunction device is provided. The heterojunction device includes a silicon (Si) substrate; and a film of silicon carbide (SiC) deposited on a surface of the Si substrate. The SiC has a Si:C ratio that increases or decreases from a SiC surface in contact with the Si substrate to an opposing SiC surface that is not in contact with the Si substrate.

Abstract: A nitride semiconductor device is provide, the nitride semiconductor device including: an epitaxial layer; and an ion implantation layer that is provided on the epitaxial layer over a continuous depth range that extends over 100 nm or longer, and has a P type doping concentration equal to or higher than 1×1017 cm?3, wherein the ion implantation layer has a region with a crystal defect density equal to or lower than 1×1016 cm?3, the region being located in a range which is on an upper-surface-side of an interface between the epitaxial layer and the ion implantation layer, and is within 100 nm from the interface.

Abstract: An optical sensor assembly is provided in which a dark mirror coating is used to suppress stray light in the form of both unwanted reflections from non-optically active regions of the sensor assembly surface and unwanted transmission of light into the surface region of the sensor assembly. The sensor assembly includes an image sensor positioned in a substrate adjacent to substrate surface areas that are not optically active. A dark mirror coating covering those surface areas significantly reduces reflections from non-optically active surface regions and improves image sensor performance in terms of signal-to-noise ratio and reduction in the appearance of “ghost” images, in turn enhancing the accuracy and precision of the sensor. The dark mirror coating may in the alternative, or in addition, be positioned underneath an optical filter, depending on the structure, material, and requirements of a particular sensor assembly.

Abstract: A packaging device including a first semiconductor device, a thermal dissipating component, an encapsulation layer, a via, and a pad. The first semiconductor device includes a substrate, an active region, and an electrode. The active region is disposed between the substrate and the electrode. The substrate has a first surface opposite to the active region, and the electrode has a second surface opposite to the active region. The thermal dissipating component is disposed on the first surface of the substrate. The encapsulation layer encloses the second surface of the electrode and a part of the thermal dissipating component, such that another part of the thermal dissipating component is exposed by the encapsulation layer. The pad is disposed on the encapsulation layer. The via is disposed in the encapsulation layer and connects the pad to the electrode.