Abstract: A temperature reading from a thermal sensor connected to a memory device is determined. The memory device comprises a plurality of memory cells. At least one of a logical capacity criterion or a physical capacity criterion is determined based on the temperature reading from the thermal sensor. Responsive to determining that at least one of the logical capacity of a first data block of the plurality of memory cells configured as a first memory type satisfies the logical capacity criterion or a physical capacity of the first data block of the plurality of memory cells configured as the first memory type satisfies the physical capacity criterion, data from the first data block is migrated to a second data block of the plurality of memory cells configured as a second memory type.

Abstract: Methods, systems, and devices for valid data aware media reliability scanning are described. An apparatus may include a memory array comprising a plurality of blocks and a controller coupled with the memory array. The controller may be configured to select a block of the plurality of blocks for a scan operation to determine a margin of reliability for a first set of data stored in the block. The controller may identify information associated with a status of a validity of sub-blocks of the first set of data in the block. The controller may determine a first subset of the sub-blocks storing valid data of the first set of data and a second subset of sub-blocks that are invalid based on identifying the information. The controller may perform the scan operation on the first subset of sub-blocks and not on the second subset of sub-blocks in the block.

Abstract: Methods, systems, and devices for one or more clock domain crossing queues are described. A queue can receive, from a first clock domain, a first command to store data in the queue. The queue can store the data at a first location indicated by a first pointer. The queue can receive, from the first clock domain, a second command to cause the second clock domain to retrieve the data from the queue. The queue can generate, based on receiving the second command, a third command synchronized with a clock of the second clock domain and to cause the second clock domain to retrieve the data. The queue can retrieve the data from the first location in the queue indicated by a second pointer associated with retrieving data based at least in part on generating the third command. The queue can transmit, to the second clock domain, the data.

Abstract: According to one embodiment, a memory system determines a write destination block and a write destination location in the write destination block to which write data is to be written, and notifies a host of an identifier of the write data, a block address of the write destination block, and an offset indicative of the write destination location. The memory system retrieves the write data from a write buffer of the host, and writes the write data to the write destination location. In a case where a read command to designate a physical address of first data is received before a write operation of the first data is finished, the memory system reads the first data from the write buffer of the host.

Abstract: Provided herein may be a memory system and a method of operating the memory system. The memory system may include a memory device including a plurality of memory blocks, and a memory controller configured to: manage an accumulated erase count value and an open block erase count value of each of the plurality of memory blocks, and select a target memory block on which a program operation is to be performed based on the accumulated erase count value and the open block erase count value of each of the plurality of memory blocks.

Abstract: A data storage apparatus may include a storage and a controller configured to operate in a throttling mode including a first performance mode and a second performance mode based on measured temperature of the storage. The controller comprises a performance adjusting component configured to determine target performance of the first performance mode based on at least one of temperature of the storage and the number of entries into the second performance mode when the temperature of the storage is greater than or equal to a first threshold value.

Abstract: A data restoration system including a data management server. The data management server receives one or more data restoration requests for restoring a plurality of data blocks. The data management server determines, based on metadata associated with the data blocks, a first subset of warm data blocks corresponding to warm-tier data and a second subset of cold data blocks corresponding to cold-tier data. The data management server retrieves the warm data blocks in the first subset and restores the warm data blocks in the first subset. The data management server groups the cold data blocks based in part on storage times of the cold data blocks to generate a plurality of cold-tier data retrieval requests. The data management server retrieves the cold data blocks by batches, each batch corresponding to one of the cold-tier data retrieval requests. The data management server restores the cold data blocks in the second subset.

Abstract: A method for performing pipeline-based accessing management in a storage server and associated apparatus are provided. The method includes: in response to a request of writing user data into the storage server, utilizing a host device within the storage server to write the user data into a storage device layer of the storage server and start processing an object write command corresponding to the request of writing the user data with a pipeline architecture of the storage server; utilizing the host device to input metadata corresponding to the user data into at least one pipeline within the pipeline architecture; and utilizing the host device to cache the metadata with a first cache module of the pipeline, for controlling the storage server completing the request without generating write amplification of the metadata, wherein the first cache module is a hardware pipeline module outside the storage device layer.

Abstract: A computer system includes a translation lookaside buffer (TLB) and a processor. The TLB comprises a first TLB array and a second TLB array, and stores entries comprising virtual address information and corresponding real address information. The processor is configured to receive a first virtual address for translation, and to concurrently determine if the TLB stores a physical address associated with the first virtual address based on a first portion and a second portion of the first virtual address. The first portion is associated with a first page size and the second portion is associated with a second page size (different from the first page size). The first portion is used to perform lookup in either one of the first TLB array and the second TLB array and the second portion is used for performing lookup in other one of the first TLB array and the second TLB array.

Abstract: There is provided a data processing apparatus and method for storing a plurality of prediction cache entries in a prediction cache with associativity greater than one comprising a plurality of prediction cache ways, each of the plurality of prediction entries defining an association between a prediction cache lookup address and target information; and storing a plurality of stream entries, each stream entry corresponding to a sequence of prediction cache lookup addresses and comprising: a stream identifier defined by two or more sequential prediction cache lookup addresses of the sequence, and a plurality of sequential way predictions, each way prediction of the plurality of sequential way predictions defining, for a given position in the sequence of prediction cache lookup addresses, a prediction cache way to be looked up in the prediction cache to identify a prediction entry associated with the prediction cache lookup address at the given position in the sequence.

Abstract: One embodiment provides a system which facilitates operation of a storage system. During operation, the system receives, by a storage engine, a request to write data to a hard disk drive. The system determines metadata associated with the data. The system stores the metadata in a volatile memory associated with the storage engine. The system identifies a physical address in a first non-volatile solid-state memory to which to write the metadata, wherein the first non-volatile solid-state memory is accessible via a controller of the hard disk drive. The system writes the metadata to the first non-volatile solid-state memory based on the physical address. The system writes the data to the hard disk drive.

Abstract: Aspects of a storage device are provided which use flow control to prevent stalling during processing of read requests for a large read command. A controller of the storage device receives a read command for data from a host device, stores in a queue read requests for a portion of the data, and reads the portion of the data from a memory based on the read requests. The controller may store other read requests in the queue for other portions of the data when a number of read requests in the queue does not meet a threshold. Otherwise, the controller refrains from storing other read requests in the queue for other portions of the data when the number of read requests in the queue meets the threshold. The controller may operate similarly with subsequent sequential commands, but may continue to store read requests in the queue for subsequent random commands.

Abstract: Apparatuses and methods for commands to perform wear leveling operations are described herein. An example apparatus may include a memory configured to receive a wear leveling command and to perform a wear leveling operation responsive to the wear leveling command. The memory may further be configured to recommend a wear leveling command be provided to the memory responsive to a global write count exceeding a threshold. The global write count may be indicative of a number of write operations performed by the memory since the memory performed a wear leveling operation.

Abstract: Storage blocks are managed. For instance, a set of write parameters and a set of deletion parameters are obtained related to a target storage block. In response to the set of write parameters matching the set of deletion parameters, a first data length is obtained for the target storage block, the first data length being determined in response to receiving a write request for the target storage block. Further, reclaim information is determined related to the target storage block based on the first data length and the set of deletion parameters. It is thus possible to reduce times of scanning the entire object table to determine whether there is an object referring to the storage block, thereby reducing the time consumed by the verification process and improving the reclaiming speed of storage blocks.

Abstract: A first operation is performed on a first portion of a plurality of data blocks. A request is received to perform a second operation associated with the plurality of data blocks. A rate of performance of the first operation on the first portion of the plurality of data blocks is determined. The second program operation is performed on a second portion of the plurality of data blocks based on the rate of performance of the first operation on the first portion of the plurality of data blocks.

Abstract: Processing requests may include: receiving a write request from a host at a first node of a system; and servicing the write comprising assigning, by the first node, a sequence identifier to the write request, wherein the sequence identifier is included in a subsequence of identifiers only assignable by the first node, performing in parallel a first operation that stores first data written by the write request in a cache, a second operation that stores a descriptor for the write request in the cache, and a third operation that sends the descriptor (including the sequence identifier) to a peer node of the system; determining by the first node that the first, second and third operations have successfully completed; and responsive to determining the first, second and third operations have successfully completed, sending an acknowledgement from the first node to a host indicating successful completion of the write request.

Abstract: An apparatus comprises a cache comprising cache entries, each cache entry storing cached information and an entry usefulness value indicative of usefulness of the cached information. Base usefulness storage circuitry stores a base usefulness value. Cache replacement control circuitry controls, based on a usefulness level determined for a given cache entry, whether the given cache entry is selected for replacement. The cache replacement control circuitry determines the usefulness level for the given cache entry based on a difference between the entry usefulness value specified by the given cache entry and the base usefulness value stored in the base usefulness storage circuitry.

Abstract: A data processing system includes multiple processing units all having access to a shared memory system. A processing unit includes a lower level cache configured to serve as a point of systemwide coherency and a processor core coupled to the lower level cache. The processor core includes an upper level cache, an execution unit that executes a store-conditional instruction to generate a store-conditional request that specifies a store target address and store data, and a flag that, when set, indicates the store-conditional request can be completed early in the processor core. The processor core also includes completion logic configured to commit an update of the shared memory system with the store data specified by the store-conditional request based on whether the flag is set.

Abstract: One disclosed embodiment includes a method for memory management. The method includes receiving a first request to clear one or more entries of a translation lookaside buffer (TLB), receiving a second request to clear one or more entries of the TLB, bundling the first request with the second request, determining that a processor associated with the TLB transitioned to an inactive mode, and dropping the bundled first and second requests based on the determination.

Abstract: A storage system and method for enabling partial defragmentation are provided. In one embodiment, a storage system comprises a memory and a controller. The controller is configured to receive an indication from a host that the host will be reading from a portion of the memory in a burst mode; determine whether a fragmentation level of the portion of the memory is above a threshold; and in response to determining that the fragmentation level of the portion of the memory is above the threshold, perform a defragmentation of the portion of the memory prior to reading data stored in the portion of the memory. Other embodiments are provided.