Patents Examined by Hong C Kim
  • Patent number: 11132262
    Abstract: An application may store data to a dataset comprising a plurality of volumes stored on a plurality of storage systems. The application may request a dataset image of the dataset, the dataset image comprising a volume image of each volume of the dataset. A dataset image manager operates with a plurality of volume image managers in parallel to produce the dataset image, each volume image manager executing on a storage system. The plurality of volume image managers respond by performing requested operations and sending responses to the dataset image manager in parallel. Each volume image manager on a storage system may manage and produce a volume image for each volume of the dataset stored to the storage system. If a volume image for any volume of the dataset fails, or a timeout period expires, a cleanup procedure is performed to delete any successful volume images.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: September 28, 2021
    Assignee: NetApp Inc.
    Inventors: Stephen Wu, Prathamesh Deshpande, Manan Patel
  • Patent number: 11132127
    Abstract: System on a Chip (SoC) devices include two packetized memory buses for conveying local memory packets and system interconnect packets. In an in-situ configuration of a data processing system two or more SoCs are coupled with one or more hybrid memory cubes (HMCs). The memory packets enable communication with local HMCs in a given SoC's memory domain. The system interconnect packets enable communication between SoCs and communication between memory domains. In a dedicated routing configuration each SoC in a system has its own memory domain to address local HMCs and a separate system interconnect domain to address HMC hubs, HMC memory devices, or other SoC devices connected in the system interconnect domain.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: September 28, 2021
    Assignee: Micron Technology, Inc.
    Inventor: John D. Leidel
  • Patent number: 11132261
    Abstract: An application may store data to a dataset comprising a plurality of volumes stored on a plurality of storage systems. The application may request a dataset image of the dataset, the dataset image comprising a volume image of each volume of the dataset. A dataset image manager operates with a plurality of volume image managers in parallel to produce the dataset image, each volume image manager executing on a storage system. The plurality of volume image managers respond by performing requested operations and sending responses to the dataset image manager in parallel. Each volume image manager on a storage system may manage and produce a volume image for each volume of the dataset stored to the storage system. If a volume image for any volume of the dataset fails, or a timeout period expires, a cleanup procedure is performed to delete any successful volume images.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: September 28, 2021
    Assignee: NetApp Inc.
    Inventors: Stephen Wu, Prathamesh Deshpande, Manan Patel
  • Patent number: 11113202
    Abstract: A memory system includes: a memory device including a memory block, a page buffer, and first and second memory dies; a write buffer suitable for temporarily storing first and second data; a program managing unit suitable for controlling the memory device to sequentially perform first and second program operations on the memory block with the first and second data; a buffer managing unit suitable for managing the write buffer based on a scatter-gather scheme; a failure processing unit suitable for forcing the second program operation to fail, when the first program operation is a failure; and an error handling unit suitable for controlling the program managing unit to perform the first and second program operations again for the first and second data that are temporarily stored in the write buffer when the second program operation is forced to fail.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: September 7, 2021
    Assignee: SK hynix Inc.
    Inventors: Hoe-Seung Jung, Joo-Young Lee
  • Patent number: 11113214
    Abstract: An apparatus for memory management a high-speed fabric controller and a memory controller connected between a high-speed memory and a processor. The memory controller is configured to control processor access to the high-speed memory over a memory bus between the processor and the high-speed memory. The apparatus includes a high-speed data connection between the memory controller and the high-speed fabric controller and a data connection between a tier of persistent data storage and the high-speed fabric controller. The high-speed fabric controller is configured to control data transfers between the tier of persistent data storage over and the high-speed memory independent of the processor.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: September 7, 2021
    Assignee: LENOVO Enterprise Solutions (Singapore) PTE. LTD
    Inventors: Jeffrey R. Hamilton, Sumanta K. Bahali, Peter R. Seidel, Brian E. Bigelow, Juan Q. Hernandez
  • Patent number: 11093409
    Abstract: Methods, systems, and computer-readable media for augmenting storage functionality using emulation of storage characteristics are disclosed. An access request for a data set is received. The access request is formatted according to a first protocol associated with a first data store, and the first data store is associated with first storage characteristics. The access request is translated into a translated access request. The translated access request is formatted according to a second protocol associated with a second data store, and the second data store is associated with second storage characteristics differing at least in part from the first storage characteristics. The translated access request is sent to the second data store. The translated access request is performed by the second data store on the data set using emulation of one or more of the first storage characteristics not included in the second storage characteristics.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: August 17, 2021
    Assignee: Amazon Technologies, Inc.
    Inventors: Gracjan Maciej Polak, Kanika Kalra, Vinayak Sundar Raghuvamshi, Syed Sajid Nizami, Per Weinberger, Amit Chhabra, Chaiwat Shuetrakoonpaiboon, Chen Zhou, Muhammad Usman, Jacob Shannan Carr, Nimit Kumar Garg, Jazarine Jamal, Reza Shahidi-Nejad
  • Patent number: 11074172
    Abstract: An embodiment of a package apparatus may include technology to control a first persistent storage media of the electronic storage, control a second persistent storage media of the electronic storage, wherein the second persistent storage media includes one or more of a faster access time and a smaller granularity access as compared to the first persistent storage media, store a logical-to-physical table in the second persistent storage media, and, in response to a data copy command, update an entry in the logical-to-physical table corresponding to a destination logical block address for the data copy command to point to a same physical address as a source logical block address for the data copy command. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: January 10, 2019
    Date of Patent: July 27, 2021
    Assignee: Intel Corporation
    Inventor: Sanjeev Trika
  • Patent number: 11068204
    Abstract: A memory device and an access method applied to the memory device are provided. The memory device is electrically connected to a host, and the memory device includes a memory circuit and a memory controller. The memory circuit includes a first memory array and a second memory array. The first memory array and the second memory array respectively provide a first physical space and a second physical space. The memory controller receives an access command from the host. The memory controller performs the access command to the first physical space when the access command is a first type of command, and the memory controller performs the access command to the second physical space when the access command is a second type of command.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: July 20, 2021
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventor: Yi-Chun Liu
  • Patent number: 11055010
    Abstract: One example provides a method of migrating a data partition from a first storage cluster to a second storage cluster, the method including determining that the data partition meets a migration criteria for migrating from the first storage cluster to the second storage cluster, on the first storage cluster, preparing partition metadata to be transferred, the partition metadata describing one or more streams within the data partition and one or more extents within each stream, transferring the partition metadata from the first storage cluster to the second storage cluster, directing new transactions associated with the data partition to the second storage cluster, including while the one or more extents reside at the first storage cluster, on the first storage cluster, changing an access attribute of the one or more extents within the data partition to read-only, and on the second storage cluster, performing new ingress for the data partition.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: July 6, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Rushi Srinivas Surla, Maneesh Sah, Shane Kumar Mainali, Wei Lin, Girish Saini, Arild Einar Skjolsvold
  • Patent number: 11055229
    Abstract: A memory system includes a memory device including a plurality of memory cells, and a memory controller configured to control the memory device. The memory controller includes a random number generator configured to generate a random number based on read data from the memory device, and an address translation module configured to generate a key based on the random number and to translate a first address into a second address by performing a calculation on the first address and the key.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: July 6, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Eun Chu Oh
  • Patent number: 11042447
    Abstract: One or more processors scan to identify component resources of a record retention system and determine relationships among the component resources and data stored on the component resources. Rules corresponding to retention of record data stored on the component resources are received, and a deletion action is determined in response to receiving a request by a user for deletion of record data from the record retention system and the rules corresponding to the retention of data. The one or more processors perform the deletion action on the user's record data associated with the request and compliant with the rules corresponding to the retention of the data among the component resources of the record retention system, and the one or more processors record the deletion action and information associated with the deletion action in a deletion log of the record retention system.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: June 22, 2021
    Assignee: International Business Machines Corporation
    Inventors: Sharif Tarequr Rahman, Long Wang, Anca Sailer
  • Patent number: 11023382
    Abstract: Implementations of using tiles for caching are detailed In some implementations, an instruction execution circuitry executes one or more instructions, a register state cache coupled to the instruction execution circuitry holds thread register state in a plurality of registers, and backing storage pointer storage stores a backing storage pointer, wherein the backing storage pointer is to reference a state backing storage area in external memory to store the thread register state stored in the register state cache.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: June 1, 2021
    Assignee: Intel Corporation
    Inventors: Raanan Sade, Jason Brandt, Mark J. Charney, Joseph Nuzman, Leena Puthiyedath, Rinat Rappoport, Vivekananthan Sanjeepan, Robert Valentine
  • Patent number: 11010089
    Abstract: The present disclosure generally relates to creating virtualized block storage devices whose data is replicated across isolated computing systems to lower risk of data loss even in wide-scale events, such as natural disasters. The virtualized device can include at least two volumes, each of which is implemented in a distinct computing system. Due to separation between volumes, replication lag may occur, in which data persisted to a first volume is not immediately persisted to a second volume. Such lag can increase a potential for data loss in the event that the first volume fails. Embodiments of the present disclosure relate to managing data loss risk by determining an expected maximum difference between the data stored at the two volumes, in a manner that does not require decrypting the data written to the volumes or perfect knowledge of the state of the distributed system at a single point.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: May 18, 2021
    Assignee: Amazon Technologies, Inc.
    Inventors: Romain Benoit Seguy, Rahul Upadhyaya, Kiran-Kumar Muniswamy-Reddy, Wells Lin, Divya Ashok Kumar Jain, William Zaharchuk
  • Patent number: 10997071
    Abstract: Devices and techniques for enhanced flush transfer efficiency in a storage device are described herein. A flush trigger for a user data write can be identified. Here, user data corresponds to the user data write and was stored in a buffer. The size of the user data stored in the buffer is smaller than a write width for a storage device subject to the write. The difference ins the user data size in the buffer and the write width is buffer free space. Additional data can be marshalled in response to the identification of the flush trigger. Here, the additional data size is less than or equal to the buffer free space. The user data and the additional data can then be written to the storage device.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: May 4, 2021
    Assignee: Micron Technology, Inc.
    Inventor: David Aaron Palmer
  • Patent number: 10970227
    Abstract: A data processing apparatus is provided, comprising a processor configured to execute a process, in particular with at least one thread, a memory management unit component configured to access a page table, and a page fault handler configured to handle page faults by triggering a page fault in response to detecting one of a plurality of predefined bit patterns in the page table, and by assigning a different page fault operation for the process, in particular with the at least one thread, to each of the plurality of predefined bit patterns.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: April 6, 2021
    Assignee: Huawei Technologies Co., Ltd.
    Inventor: Jani Kokkonen
  • Patent number: 10970231
    Abstract: Provided are a computer product, method, and system to virtualize target system storage resources as virtual target storage resources. Target storage resources available at a target system are discovered over a network. A configuration is determined of virtual target storage resources mapping to the target storage resources for a host node. The configuration is registered with a virtual target. The configuration maps the virtual target storage resources to the target storage resources at the target system and an access control list of the host node allowed to access the virtual target storage resources. A query is received from the host node for the target storage resources the host node is permitted to access according to the access control list. Host discovery information is returned to the requesting host node indicating the virtual target storage resources the requesting host node is provisioned to access from the virtual target.
    Type: Grant
    Filed: January 4, 2019
    Date of Patent: April 6, 2021
    Assignee: Intel Corporation
    Inventors: Jay E. Sternberg, Phil C. Cayton, James P. Freyensee, Dave B. Minturn
  • Patent number: 10963385
    Abstract: A method for performing pipeline-based accessing management in a storage server and associated apparatus are provided. The method includes: in response to a request of writing user data into the storage server, utilizing a host device within the storage server to write the user data into a storage device layer of the storage server and start processing an object write command corresponding to the request of writing the user data with a pipeline architecture of the storage server; utilizing the host device to input metadata corresponding to the user data into at least one pipeline within the pipeline architecture; and utilizing the host device to cache the metadata with a first cache module of the pipeline, for controlling the storage server completing the request without generating write amplification of the metadata, wherein the first cache module is a hardware pipeline module outside the storage device layer.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: March 30, 2021
    Assignee: Silicon Motion Technology (Hong Kong) Limited
    Inventors: Guo-Fu Tseng, Cheng-Yue Chang, Kuan-Kai Chiu
  • Patent number: 10956080
    Abstract: A method of erasing data using a file-based protocol from a data storage apparatus for repurposing, reallocation to a new user or retirement of the data storage apparatus, the data storage apparatus comprising a memory using a file-based protocol, and the method comprises: receiving one or more signals representative of the available free space of at least one selected region of the memory; iteratively writing files to the at least one selected region of the memory using the file based protocol, wherein: at least one of the files is sized based on at least one of the received signals and the iterative writing of the files comprises writing the files in sequence such that for at least part of the sequence each file is smaller in size than the preceding file of the sequence; and wherein the files are written to collectively occupy all of the at least one selected region of the memory; and the method further comprises receiving an indication that said at least one selected region of memory is full following the
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: March 23, 2021
    Assignee: BLANCCO TECHNOLOGY GROUP IP OY
    Inventors: Pasi Kellokoski, Markus Törmä, Pekka Nurminen, Tomi Lehtola, Petri Hentunen
  • Patent number: 10949092
    Abstract: A device includes a host including a main memory, and semiconductor memory including a nonvolatile semiconductor memory, memory unit, and controller. The nonvolatile semiconductor memory stores first address information. The memory unit stores second address information as part of the first address information. The controller accesses the nonvolatile semiconductor memory based on the second address information. Third address information is stored in the main memory, and is part or all of the first address information. The controller uses the third address information when accessing the nonvolatile semiconductor memory if address information to be referred is not stored in the second address information.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: March 16, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Atsushi Kunimatsu, Kenichi Maeda
  • Patent number: 10942679
    Abstract: An operating method of a storage device which includes a plurality of banks includes receiving a write command including stream identification information from a host, allocating a bank, in which data are to be stored, from among the plurality of banks based on a striping size corresponding to the stream identification information, in response to the write command, and writing the data in the allocated bank.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: March 9, 2021
    Inventors: Jinwoo Kim, Wan-Soo Choi