Abstract: Embodiments relate to impact-based migration scheduling. An aspect includes identifying, by a migration scheduling module, a plurality of feasible destination storage devices for a migration session. Another aspect includes determining, for each of the identified destination storage devices, an impact of the migration session during the migration session. Another aspect includes determining, for each of the identified destination storage devices, an impact of the migration session after the migration session is completed. Another aspect includes selecting a destination storage device from the identified destination storage devices based on the impact of the migration session during the migration session and the impact of the migration session after the migration session is completed. Another aspect includes determining a start time and transfer rate for the migration session based on the selected destination storage device.

Abstract: A processor includes a core, a prefetcher, and a prefetcher control module. The prefetcher includes logic to make speculative prefetch requests through a memory subsystem for an element for execution by the core, and logic to store prefetched elements in a cache. The prefetcher control module includes logic to determine counts of memory accesses to two types of memory and, based upon the counts and the type of memory, reduce the speculative prefetch requests of the prefetcher.

Abstract: Systems and methods define a memory system using an abstracted memory protocol that enables virtual to physical mapping of memory address requests at an abstracted memory module. A memory abstraction unit abstracts timing and naming of memory requests from one or more clients to timing and naming at one or more memory devices. The memory abstraction unit includes abstracted memory protocol logic for interpreting the memory requests from the one or more clients. The memory abstraction unit also includes mapping logic for translating the naming defined by a memory access request by a requesting client to a virtual physical address at a selected protection zone in at least one of the one or more memory devices and memory control logic for accessing the one or more memory devices at the virtual physical address.

Abstract: According to one embodiment, a memory system includes a first memory, a second memory, a third memory, a data transmission controller, and a processing unit. The second memory is configured to store first management information to manage the first memory. The third memory is configured to be accessed at a speed higher than the second memory. The processing unit causes the data transmission controller to transmit second management information and third management information from the second memory to the third memory in a burst mode before a read process is performed on the first memory. The second management information and the third management information are related to the read process and are included in the first management information. The processing unit performs the read process on the first memory using the second management information and the third management information stored in the third memory.

Abstract: Provided are a device and method of controlling a dish cache, wherein a time of seeking a disk cache may be shortened and a hit rate of a disk cache may be increased. The device includes a main memory including a buffer cache, a flash memory including a flash cache, and a controller controlling the buffer cache and the flash cache, wherein the buffer cache and the flash cache are enabled to cache a data block stored in a disk, and the controller identifies a position where the data block is cached using metadata.

Abstract: A file system to controls access to a tape library that selectively loads and unloads a plurality of cartridges from a plurality of slots to a drive for transmitting to the file system archived data retrieved from a particular cartridge. The file system includes a cache and receives a request from a requestor to access the tape library, estimates a first data transfer rate from an anticipated tape library operation completion duration and from a capacity of cached data to be transmitted from the cache to the requestor, initiates access to the tape library, and adapts the first data transfer rate to a second data transfer rate to transmit the capacity of the cached data to the requestor throughout the anticipated tape library operation completion duration.

Abstract: A disk array system and a data processing method are provided. The data processing method is applied to the disk array system. The disk array system is a redundancy array of independent disk 0 (RAID 0) system. The disk array system includes a plurality of disks. The data processing method includes: receiving a reading command; determining whether to divide the reading command to a plurality of reading command segments according to the reading command; and assigning the reading command to a corresponding disk of the disks to read data stored in the corresponding disk accordingly when it is determined that the reading command is not divided.

Abstract: Subject matter disclosed herein relates to read and write processes of a memory device.

Abstract: A memory system includes an interface, a storage, and a controller. The interface is configured to connect to a plurality of initiators. The storage is configured to store data. The controller is configured to refer to a connection condition of the interface and transmit data to be transmitted to an initiator being connected from the storage.

Abstract: Banks within a dynamic random access memory (DRAM) are managed with virtual bank managers. A DRAM controller receives a new memory access request to DRAM including a plurality of banks. If the request accesses a location in DRAM where no virtual bank manager includes parameters for the corresponding DRAM page, then a virtual bank manager is allocated to the physical bank associated with the DRAM page. The bank manager is initialized to include parameters needed by the DRAM controller to access the DRAM page. The memory access request is then processed using the parameters associated with the virtual bank manager. One advantage of the disclosed technique is that the banks of a DRAM module are controlled with fewer bank managers than in previous DRAM controller designs. As a result, less surface area on the DRAM controller circuit is dedicated to bank managers.

Abstract: Provided are a computer program product, system, and method for data unit classification in accordance with one embodiment of the present description, in which in response to a data processing command, a storage controller classifies data units of a storage unit as either allocated to a data set or as unallocated to any data set. If allocated to a data set, the storage controller can further classify data set-allocated data units as either containing client data or metadata or as empty. In accordance with one aspect of the present description, the storage controller may bypass data processing of the data units which have not been allocated to any data set or otherwise do not contain client data or metadata. Other aspects of data unit classification in accordance with the present description are described.

Abstract: In one embodiment, a computer program product for modifying a virtual storage access method (VSAM) data set during open time, the computer program product including a computer readable storage medium having computer readable program code embodied therewith, the embodied computer readable program code including computer readable program code configured to open a VSAM data set, and computer readable program code configured to modify a VSAM control block structure for the VSAM data set while the VSAM data set is open during an open time in which static data set characteristics and/or job parameters have been defined for the VSAM data set, wherein the computer readable program code configured to modify the VSAM control block structure includes computer readable program code configured to interact with the VSAM data set within a VSAM dynamic address space using at least one of: a VSAM console interface and a VSAM programming interface.

Abstract: A method and system are disclosed for handling logical-to-physical mapping in a storage device. The method includes the storage device storing in fast access memory, such as DRAM, only a fixed-size subset of the primary mapping table in non-volatile memory, along with contiguity information of physical addresses for logical address not in the subset that are adjacent to the logical addresses in the subset. The system includes a storage device having volatile memory, non-volatile memory and a controller in communication with the volatile and non-volatile memory that is configured to carry out the method noted above.

Abstract: A storage subsystem can achieve more efficient I/O processing by enabling users to specify and pass out of band I/O hints comprising an object to be hinted, a hint type, and caching strategies associated with a hint type. A hinted object may be either a virtual device or a file. In addition to priority cache, hint types may include never-cache, sticky-cache, and volatile-cache. Hints may be passed via command-line or graphical-user interfaces.

Abstract: An integrated circuit including a cache and first and second modules. The cache is folded a predetermined number of times. The cache includes arrays and storage elements. Each of the arrays includes respective ones of the storage elements. The arrays store a cache line. The cache line includes segments of data. The segments of data are stored in two or more of the arrays. Each of the segments of data is stored in a corresponding one of the storage elements. The first module receives a first identifier of one of the segments of data and a second identifier of a set of the storage elements. The first module determines an index based on the first and second identifiers. The second module, based on the index, accesses one of the segments of data from the two or more of the arrays and outputs the one of the segments of data.

Abstract: In one embodiment, a method includes receiving a request to establish a Peer-to-Peer Remote Copy (PPRC) relationship between a primary storage system and a secondary storage system, and copying one or more data tracks of a primary storage device in the primary storage system to the secondary storage system without copying at least one other data track of the primary storage device to the secondary storage system. The one or more data tracks of the primary storage device comprise one or more data tracks of a first characteristic. Other portions of the primary storage device comprise one or more other data tracks of a second characteristic.

Abstract: A memory controller is provided. In response to a burst read command that includes a target address, the memory controller provides, to one or more busses, data stored in memory at the target address after dummy clock cycles have occurred. The memory controller also provides a preamble on the bus(ses) during some of the dummy clock cycles. The preamble includes a data training pattern.

Abstract: A set associative cache is managed by a memory controller which places writeback instructions for modified (dirty) cache lines into a virtual write queue, determines when the number of the sets containing a modified cache line is greater than a high water mark, and elevates a priority of the writeback instructions over read operations. The controller can return the priority to normal when the number of modified sets is less than a low water mark. In an embodiment wherein the system memory device includes rank groups, the congruence classes can be mapped based on the rank groups. The number of writes pending in a rank group exceeding a different threshold can additionally be a requirement to trigger elevation of writeback priority. A dirty vector can be used to provide an indication that corresponding sets contain a modified cache line, particularly in least-recently used segments of the corresponding sets.

Abstract: Embodiments of the invention relate to cache management of sequential write storage. Cache states of cache blocks in cache storage are tracked. The tracking incudes creating a migration candidate list that organizes the cache blocks into virtual volumes. Based on determining that a cache migration threshold has been reached, at least a subset of the cache blocks are selected from the migration candidate list for migration. The selected cache blocks are ordered into a sequential order based on the migration candidate list. At least a subset of the selected cache blocks are migrated in the sequential order, the migrating including writing contents of the selected cache blocks to the sequential write storage.

Abstract: A control method to be executed by a processor included in a transmission apparatus, the control method includes receiving, from a first interface device storing first circuit data, a first version of the first circuit data at a time of coupling of the first interface device to the transmission apparatus; extracting, from a plurality of interface devices included in the transmission apparatus, second circuit data of a second interface device storing the second circuit data, where a second interface device type is a same as a first interface device type, when the second interface device exists in the plurality of interface devices and when the first version matches a second version stored in a memory, the second version being associated with the second interface device type of the second version stored in the memory; and copying the second circuit data to the first interface device.