Abstract: An apparatus including a memory having an array of blocks addressable using address bits; and a permutation circuit coupled to the memory and configured to permutate the address bits such that during a memory access blocks of data are rearranged virtually.

Abstract: A virtual machine environment in which a hypervisor provides direct memory mapped access by a virtual guest to a physical memory device. The hypervisor prevents reading from, writing to, or both, any individual register or registers while allowing unrestricted access to other registers, and without raising any abnormal condition in the guest's execution environment. For example, in one embodiment, the hypervisor can apply memory access protection to a memory page containing a restricted register so that a fault condition can be raised. When an instruction is executed, the hypervisor can intercept the fault condition and emulate the faulting guest instruction. When the emulation accesses the restricted address, the hypervisor can selectively decide whether or not to perform the access.

Abstract: Provided are method and device for managing a memory in a data stream management system (DSMS) of a portable device. The method includes moving data of a selected memory region that has a low priority to a secondary storage and storing a received data stream in the selected memory region.

Abstract: An approach for erasing data being stored in a data storage apparatus is provided. The approach may be provided e.g. as an apparatus, as a method, as a system or as a computer program. The approach comprises obtaining a sequence of uncompressible data fulfilling predetermined criteria, which predetermined criteria comprises a statistical measure indicative of compressibility or uncompressibility of the sequence of uncompressible data meeting a predetermined criterion, wherein the sequence of uncompressible data is divided into one or more blocks of uncompressible data, the sum of the sizes of the one or more blocks of uncompressible data being larger than or equal to the storage capacity of the data storage apparatus, and providing, to the data storage apparatus, the one or more blocks of uncompressible data for storage therein to overwrite the data being currently stored in the data storage apparatus.

Abstract: A RAID storage system serializes data blocks to be stored in a RAID storage array and uses a primary map table and a number of secondary map tables to relate host addresses to logical block addresses in the storage array. Secondary map tables and other metadata can be cached from the storage array. The dual or two-tier map scheme and metadata caching promote scalability.

Abstract: Banks within a dynamic random access memory (DRAM) are managed with virtual bank managers. A DRAM controller receives a new memory access request to DRAM including a plurality of banks. If the request accesses a location in DRAM where no virtual bank manager includes parameters for the corresponding DRAM page, then a virtual bank manager is allocated to the physical bank associated with the DRAM page. The bank manager is initialized to include parameters needed by the DRAM controller to access the DRAM page. The memory access request is then processed using the parameters associated with the virtual bank manager. One advantage of the disclosed technique is that the banks of a DRAM module are controlled with fewer bank managers than in previous DRAM controller designs. As a result, less surface area on the DRAM controller circuit is dedicated to bank managers.

Abstract: A storage controller coupled to a host computer is dynamically configured by a device driver executing in the host computer. The storage controller manages a logical volume for the host using a set of flash-based storage devices arranged as a redundant array of inexpensive disks (RAID). The device driver identifies a RAID type for the logical volume and a queue depth from a stream of I/O commands. For a logical volume in RAID 0, the device driver compares the queue depth to a threshold value and configures the storage controller to process the stream of I/O commands with a first path or an alternative path based on a result of the comparison. For a logical volume in RAID 5, the device driver performs a similar comparison and uses the result to direct the storage controller to use a write back or a write through mode of operation.

Abstract: A device includes a host including a main memory, and semiconductor memory including a nonvolatile semiconductor memory, memory unit, and controller. The nonvolatile semiconductor memory stores first address information. The memory unit stores second address information as part of the first address information. The controller accesses the nonvolatile semiconductor memory based on the second address information. Third address information is stored in the main memory, and is part or all of the first address information. The controller uses the third address information when accessing the nonvolatile semiconductor memory if address information to be referred is not stored in the second address information.

Abstract: An apparatus includes a device interface, a micro-sequencer, and a programmable sequence memory. The device interface may be configured to process a plurality of read/write operations to/from one or more non-volatile memory devices. The micro-sequencer may be configured to communicate with the device interface. The programmable sequence memory is generally readable by the micro-sequencer. In response to the apparatus receiving a command, (a) the micro-sequencer executes a set of instructions starting at a location in the programmable sequence memory according to the command and (b) the micro-sequencer is enabled to perform at least a portion of the command according to a protocol of the one or more non-volatile memory devices, when the one or more non-volatile memory devices are coupled to the device interface.

Abstract: A method of enabling “fast” suspend and “rapid” resume of virtual machines (VMs) employs a cache that is able to perform input/output operations at a faster rate than a storage device provisioned for the VMs. The cache may be local to a computer system that is hosting the VMs or may be shared cache commonly accessible to VMs hosted by different computer systems. The method includes the steps of saving the state of the VM to a checkpoint file stored in the cache and locking the checkpoint file so that data blocks of the checkpoint file are maintained in the cache and are not evicted, and resuming execution of the VM by reading into memory the data blocks of the checkpoint file stored in the cache.

Abstract: A storage apparatus for which a hierarchical data management system is adopted is designed so that when receiving a read request for a first logical area to which a first storage area of a first storage device in a virtual volume is allocated, whether or not to migrate data in a first storage area of the first storage device, to a storage area of a second storage device is decided according to an access frequency to the first logical area in synchronization with the read request. When it is decided that the data stored in the first storage area of the first storage device should be migrated to the storage area of the second storage device, the data is migrated to a second storage area of the second storage device and the second storage area thereof is allocated to the first logical area in the virtual volume.

Abstract: Many of the benefits of solid-state-based storage devices can be obtained, while minimizing the costs associated therewith, by write-throttling solid-state storage media in accordance with empirically derived capabilities. Untested solid-state storage media can be obtained inexpensively due to the lack of waste that is otherwise been inherent in the testing and subsequent discarding of solid-state storage media whose capabilities do not meet stringent manufacturer standards. The untested solid-state storage media is initialized through a testing procedure that empirically identifies capabilities of individual solid-state blocks, or groupings of blocks, within such solid-state storage media. Such empirically obtained capability information is then utilized to throttle the speed at which data is written to the solid-state storage media. Additionally, it can enable binning of individual solid-state blocks, or individual groupings of blocks, into bins that can comprise different performance thresholds.

Abstract: An operating method of a data storage device including nonvolatile memory devices includes making a victim block list for victim blocks for which a merge operation is to be performed and copying valid pages of the victim bocks to a merge block. The method also includes determining whether there is a victim block which has an erase-held valid page selectively erasing the victim blocks included in the victim block list, according to which victim blocks have an erase-held page, and updating the victim block list according to which victim blocks are erased.

Abstract: A memory device is provided. The memory device includes a preamble memory and a memory controller. The preamble memory is arranged to store a read preamble such that the read preamble includes a training pattern that is suitable for aligning a capture point for read data. Further, the training pattern is programmable such that the training pattern can be altered at least once subsequent to manufacture of the preamble memory. In response to a read command, the memory controller provides the read preamble stored in the preamble memory, as well as the read data.

Abstract: Described herein is a system and method for retaining deduplication of data blocks of a resulting storage object (e.g., a flexible volume) from a split operation of a clone of a base storage object. The clone may comprise data blocks that are shared with at least one data block of the base storage object and at least one data block that is not shared with at least one data block of the base storage object. The data blocks of the clone that are shared with the base storage object may be indicated to receive a write allocation that may comprise assigning a new pointer to a indicated data block. Each data block may comprise a plurality of pointers comprising a virtual address pointer and a physical address pointer. As such, data blocks of the clone comprising the same virtual address pointer may be assigned a single physical address pointer. Thus, a new physical address pointer is assigned or allocated once to a given virtual address pointer of data blocks of a clone.

Abstract: Techniques for surfacing host-side flash storage capacity to a plurality of VMs running on a host system are provided. In one embodiment, the host system creates, for each VM in the plurality of VMs, a flash storage space allocation in a flash storage device that is locally attached to the host system. The host system then causes the flash storage space allocation to be readable and writable by the VM as a virtual flash memory device.

Abstract: Techniques, including systems and methods, take frequent captures of data sets for the purpose of forensic analysis. The data set captures are taken at the block level in various embodiments. Data set captures are used to instantiate forensic storage volumes that are attached to computing instances. The computing instances can access data in the forensic storage volumes at a state corresponding to a specified capture time. A user can select different capture times to re-instantiate the forensic storage volume to see how the forensic storage volume changed between captures.

Abstract: Some implementations disclosed herein provide techniques and arrangements for recovery of data stored in memory shared by a number of processors through information stored in a cache directory. A core of a processor may initiate access (e.g., read or write) to particular data located in a first cache that is accessible to the core. In response to detecting an error associated with accessing the particular data, a location in the processor that includes the particular data may be identified and the particular data may be copied from the location to the first cache.

Abstract: A processor including a virtualization system of the processor with a memory virtualization support system to map a reference to guest-physical memory made by guest software executable on a virtual machine which in turn is executable on a host machine in which the processor is operable to a reference to host-physical memory of the host machine.

Abstract: According to an embodiment, a computer system for cache management includes a processor and a cache, the computer system configured to perform a method including receiving a first store request for a first address in the cache and receiving a first fetch request for the first address in the cache. The method also includes executing the first store request and the first fetch request, latching the first store request in a store write-back pipeline in the cache, detecting, in the processor, a conflict following execution of the first store request and the first fetch request and receiving the first store request from a recycle path including the store write-back pipeline and executing the first store request a second time.