Abstract: An apparatus include one or more DACs and a resistor divider are configured to generate a variable bias voltage VBIAS with respect to a CM voltage VCM. The CM voltage VCM is applied to a cathode of one or more thermopiles or a negative input of one or more amplifiers to prevent saturation and over range of one or more low voltage readout amplifiers and one or more ADCs.

Abstract: A digital equalizer with reduced number of multipliers for correction of the frequency responses of an interleaved analog-to-digital-converter (ADC) is disclosed. An exemplary interleaved analog to digital converter with digital equalization includes at least one composite ADC including M time-interleaved sub-ADCs, and an equalization configuration deploying a Pre-FIR transformers unit, a FIRs assembly unit, and a Post-FIR transformers unit. The FIRs assembly unit includes a finite impulse response (FIR) filter network which is operative pursuant to a Fast Filtering Algorithm as an alternative to a conventional finite impulse response network, enabling a reduction of the number of multipliers compared to conventional FIR filter-based equalization networks for ADCs.

Abstract: An analog to digital converter (ADC) is disclosed. The ADC includes a DAC which generates a first signal based on an analog input and a digital input word, and a comparator which generates a comparator output having a value corresponding with a sign of a difference between first and second signals. During a first time period, the second signal is equal to a reference signal, the first signal is equal to an analog input, and the comparator generates a first comparator output. During a second time period, the second signal is equal to the reference signal, the first signal is equal to a the analog input plus a predetermined signal, and the comparator generates a second comparator output. A SAR logic circuit generates the digital input word for the DAC based on the first and second comparator outputs.

Abstract: Compressed domain processors configured to perform operations on data compressed in a format that preserves order. The Compressed domain processors may include operations such as addition, subtraction, multiplication, division, sorting, and searching. In some cases, compression engines for compressing the data into the desired formats are provided.

Abstract: A successive approximation register (SAR) analog to digital converter (ADC) is disclosed. The SAR ADC includes: a DAC, configured to receive an analog input voltage and a digital input word, and to generate a first voltage. The SAR ADC also includes a comparator, configured to generate a second voltage based on the first voltage and a reference voltage. The second voltage has a value corresponding with a sign of the difference between the first voltage and the reference voltage. The SAR ADC also includes an SAR logic circuit configured to receive the second voltage from the comparator, and to generate the digital input word for the DAC. The SAR logic is further configured to generate a digital output word representing the value of the analog input voltage, where the digital output word of the SAR logic has a greater number of bits than the digital input word of the DAC.

Abstract: Electronic devices may be provided with antenna arrays and wireless circuitry for handling wireless communications in satellite communications bands and other frequency bands of interest. A portable electronic device may have a housing with a peripheral edge. An array of antennas in the portable device may extend along the peripheral edge and may be coupled (directly or indirectly) to wireless circuitry that transmits and receives satellite communications signals and/or other wireless communications signals. The antennas may include dipole antennas. The dipole antennas may include edge dipole antennas with straight arms that extend parallel to one or more peripheral housing edges. Additionally or alternatively, the dipole antennas may include corner dipole antennas at the corners of the housing. The corner dipole antennas may have arms with bent tips. A ground plane in the center of the electronic device may serve as a reflector for the peripheral dipole antennas.

Abstract: An analog-to-digital conversion apparatus includes a controller. The controller is configured to execute first control processing to cause the selection circuit of each of the circuit sets to perform switching which involves cyclically changing an analog signal to be selected at sampling timings with a predetermined time difference, and second control processing to calculate a digital data item at a reference sampling timing for each of the analog signals based on digital data items obtained from the analog-to-digital converter of the plurality of circuit sets, in accordance with the digital data items with the predetermined time difference, the sampling timings, and the time difference.

Abstract: An object of the present invention is to efficiently compress a plurality of kinds of data series with different sampling rates. A data compression device has a grouping unit and a compression unit. The grouping unit groups a plurality of kinds of data series with different sampling rates. The compression unit compresses the data series grouped by the grouping unit.

Abstract: A method of converting 10-bit pixel data (e.g. 10:10:10:2 data) into 8-bit pixel data involves converting the 10-bit values to 8-bits using a technique that is selected dependent upon the values of the MSBs of the 10-bit values and setting the value of an HDR flag dependent upon the values of the MSBs. The HDR flag is appended to the 3-bit channel.

Abstract: A phased-locked loop (PLL) includes a first oscillator supplying a first oscillator signal with a first jitter component and a second oscillator supplying a second oscillator signal with a second jitter component. The second jitter component is higher than the first jitter component. A selector circuit selects either the first oscillator signal or the second oscillator signal as the PLL output signal. The first oscillator signal and the second oscillator signal may have different frequencies with the lower frequency signal having more jitter. The oscillator producing the signal with less jitter utilizes more power. A continuous time delta-sigma modulator analog-to-digital converter (ADC) receives the PLL output signal as an input clock signal. A high gain setting of an amplifier supplying an input signal to the ADC selects a lower jitter signal input clock signal and a lower gain setting selects a higher jitter input clock signal.

Abstract: Disclosed is an analog-to-digital converter with an adjustable operation frequency for noise reduction. The operation frequency of the analog-to-digital converter is adjustable, and if an input signal or a circuit is affected by a noise, the noise can be reduced by spreading the frequency distribution of the noise. A clock generator generates a clock signal for controlling the operation frequency of the analog-to-digital converter. Additionally, a clock controller receives a setting signal and a counting signal, controls the clock generator, and adjusts the frequency of the clock signal. In addition, a counter counts the number of periods of the clock signal, and generates the counting signal. Furthermore, a selecting signal makes the frequency of the clock signal gradually increase or decrease with time, thereby allowing change rate or change amount of the frequency of the clock signal to be adjustable.

Abstract: An apparatus for interpolating between a first and a second signal is provided. The apparatus includes a plurality of interpolation cells coupled to a common node of the apparatus. Further, the apparatus includes a control circuit configured to supply, based on a control word, respective selection signals to each of the plurality of interpolation cells. At least one of the plurality of interpolation cells is configured to couple the common node to a first potential if the first signal and the second signal are both at a first signal level, couple the common node to a second potential, which is different from the first potential, if the first signal and the second signal are both at a second signal level, which is different from the first signal level, and to decouple the common node from at least one of the first potential and the second potential if the first signal and the second signal are at different signal levels.

Abstract: An information processing device includes: an apparatus main body; and a display mechanism that is provided to be displaceable with respect to the apparatus main body, is provided with an antenna used to perform communication with a mobile terminal, and is configured to display information. The apparatus main body is not located in a place where the display mechanism extends upwards and downwards the display mechanism in a state in which the display mechanism is displaced with respect to the apparatus main body.

Abstract: The present invention aims to reduce power consumption in an ADC that performs AD conversion of a single-ended signal. A pair of sampling capacitors samples the single-ended signal. After the single-ended signal has been sampled, the connection control unit performs positive-side connection control of connecting both ends of one of the pair of sampling capacitors across a positive-side signal line and a predetermined ground potential and performs negative-side connection control of connecting both ends of the other of the pair of sampling capacitors across a negative-side signal line and the predetermined ground potential. A conversion unit converts a differential signals from the positive-side signal line and the negative-side signal line that have respectively undergone the positive-side connection control and the negative-side connection control into a digital signal.

Abstract: A satellite system can include one or more satellites that orbit the Earth. The one or more satellites may have satellite buses that support antenna arrays. The antenna arrays may include space fed arrays. Each space fed array may have an antenna feed array and an inner array that is coupled to a direct radiating array. The direct radiating array may operate in the same satellite band as the space fed array, or upconversion and downconversion circuitry may be used to communicatively couple a direct radiating array that operates in a different satellite band to the space fed array. The satellites may have peripheral walls with corner fittings that can be selected to provide the satellite bus with particular leg strengths. This can reduce overall mass of the satellites in a payload fairing while accommodating different types of antenna arrays.

Abstract: An analog-to-digital converter has first and second comparators and an interpolation comparator. The first comparator receives an input signal and a comparison signal, and generates an output as a function of the input signal and the comparison signal. The second comparator receives the input signal and a second comparison signal (different from the first comparison signal), and generates a second output as a function of the input signal and the second comparison signal. The interpolation comparator, operatively connected to the first and second comparators, receives the first and second outputs, and generates a third output based on relative timing of the first and second outputs.

Abstract: A method is used in managing inline data compression and deduplication in storage systems. A block of data from data stored in a cache of a storage system is identified based on entropy. Entropy of the block of data is compared with a first threshold value. Based on the comparison, the block of data is either deduplicated or compressed without deduplication.

Abstract: This is directed to connecting two or more elements using an intermediate element constructed from a material that changes between states. An electronic device can include one or more components constructed by connecting several elements. To provide a connection having a reduced or small size or cross-section and construct a component having high tolerances, a material can be provided in a first state in which it flows between the elements before changing to a second state in which it adheres to the elements and provides a structurally sound connection. For example, a plastic can be molded between the elements. As another example, a composite material can be brazed between the elements. In some cases, internal surfaces of the elements can include one or more features for enhancing a bond between the elements and the material providing the interface between the elements.

Abstract: Embodiments of the present invention are directed to a computer-implemented method for data compression. The method includes monitoring data, from a data stream, stored in an input buffer and system memory of a data compression system. The method further includes choosing an encoding scheme based in part upon the amount of data in the input buffer. The method further includes encoding data using the encoding scheme to compress the data from the data stream. The method further includes reevaluating, during the data stream, an encoding scheme choice based in part upon the amount of data in the input buffer.

Abstract: System and methods for input path matching in pipelined continuous-time Analog-to Digital Converters (ADCs), including pipelined Continuous-Time Delta Sigma Modulator (CTDSM) based ADCs, includes an input delay circuit disposed in a continuous-time input path from an input of an analog input signal to a first summing circuit of the continuous-time ADC. At least one digital delay line is disposed between an output of an earlier stage sub-ADC (of a plurality of pipelined sub-ADCs) and a sub-digital-to-analog converter (DAC) that is coupled to the first summing circuit, and between the earlier stage sub-ADC and a digital noise cancellation filter. The digital delay line(s) is configured to enable calibration of delay of output of the earlier stage sub-ADC provided to the sub-DAC and the digital noise cancellation filter in accordance with process variations of the input delay match circuit to minimize residue output at first summing circuit.