Abstract: An analog to digital converter (ADC) is disclosed. The ADC includes a DAC which generates a first signal based on an analog input and a digital input word, and a comparator which generates a comparator output having a value corresponding with a sign of a difference between first and second signals. During a first time period, the second signal is equal to a reference signal, the first signal is equal to an analog input, and the comparator generates a first comparator output. During a second time period, the second signal is equal to the reference signal, the first signal is equal to a the analog input plus a predetermined signal, and the comparator generates a second comparator output. A SAR logic circuit generates the digital input word for the DAC based on the first and second comparator outputs.

Abstract: The present invention provides a phase shifter assembly for an array antenna, comprising: a first level phase shifter, wherein the first level phase shifter is configured to control the phases of a plurality of sub-arrays of the array antenna, where each sub-array comprises one or more radiating elements; a second level phase shifter, wherein the second level phase shifter is configured to proportionally change the phases of the radiating elements in the corresponding sub-arrays; and a power divider, wherein the power divider is connected between the first level phase shifter and the second level phase shifter. The phase shifter assembly has the advantages of both a distributed phase shifter network and a lumped phase shifter network. Specifically, the phase shifter assemblies can independently control the phases of the radiating elements in the array to obtain better sidelobe suppression.

Abstract: Embodiments of the disclosure can provide digital-to-analog converter (DAC) termination circuits. A single or multiple parallel impedance networks can be coupled to a DAC to reduce the DAC's AC impedance, increase the DAC speed, and reduce the DAC settling time. The parallel impedance networks can be coupled to one or more of the DAC terminals in termination specific cases, or to nodes within the DAC. In an example, one-sided T-termination can be used with a single termination impedance path coupled in parallel with the DAC terminals, for reducing AC impedance at the DAC reference terminals, increasing speed, and reducing settling time. In an example, multiple impedance networks can be used in an H-bridge termination solution, which can be useful for high resolution DACs with or within a high voltage range.

Abstract: The present disclosure a switched-mode power supply using a reconfigurable delta-signal modulator (DSM). The switched-mode power supply comprises, a current sensing unit configured to determine an operation mode on the basis of a result of sensing a current of an output terminal; a compensator configured to output a compensation signal by amplifying a difference value between an output voltage and a reference voltage; a reconfigurable DSM configured to output a digital signal by noise-shaping the compensation signal; a power switch unit switched by the digital signal to output an output voltage; and an attenuator configured to supply a feedback voltage of the output voltage attenuated by a voltage divider to the compensator.

Abstract: A data compression system can include a compression unit comprising a single chaotic system having an identified initial condition that produces a desired output sequence of data corresponding to a data set being stored. The single chaotic system can be identified using a chain of controlled nonlinear systems and a dynamical search technique to match the output, in sequence over consecutive time intervals with the chain of the controlled nonlinear systems.

Abstract: A Planar Inverted-F Antenna, PIFA, comprises a sheet of conductive material including first, second, third and fourth contiguous sections, the first and third sections extending orthogonally away from the second section and the fourth section extending away from the third section. The sections are folded relative to one another to define a volume with a height of the second section, a width of the second section and a depth of the third section extending away from the second section. A supporting pin and a feed pin extend from the second section along an outer edge. A supporting leg extends from either the third or fourth sections, the supporting leg lying outside the plane of the supporting pin to support the PIFA when mounted on a printed circuit board, while allowing components to at least partially occupy the volume under the PIFA.

Abstract: An antenna structure includes a ground plane in a first metal layer of an integrated circuit (IC) package, a patch in a second metal layer of the IC package, a cavity structure between the ground plane and the patch, and a high-k dielectric layer between the ground plane and the patch.

Abstract: A programmable digital-to-analog converter includes an analog circuit that converts a binary word into a value of analog voltage and a digital circuit that supplies the binary word starting from a maximum value decremented by a decrement value.

Abstract: A method of performing analog-to-digital conversion using a successive approximation (SAR) analog-to-digital converter (ADC). A previous digital output is compared to a range based on the first M bits of the previous digital output. If the previous digital output is within that range, a digital-to-analog converter (DAC) of the SAR ADC is preloaded with the first M bits of the previous digital output, prior to commencing bit trials. If the previous digital output is outside of that range, an offset is applied to the first M bits of the previous digital output and the DAC is preloaded based on the M bits and the offset, prior to performing bit trials. This method reduces the possibility of the next input being outside of a further range defined by the preload.

Abstract: Compressed domain processors configured to perform operations on data compressed in a format that preserves order. The Compressed domain processors may include operations such as addition, subtraction, multiplication, division, sorting, and searching. In some cases, compression engines for compressing the data into the desired formats are provided.

Abstract: A semiconductor device includes; a loop filter that receives a differential analog signal and generates a residue signal indicating an error between an analog input signal and an feedback signal, a first ADC that receives the residue signal and generates a first digital representation, a second ADC that receives the analog input signal and generates a second digital representation corresponding to the analog input signal, and a digital to analog converter (DAC) that receives a sum of the first digital representation and the second digital representation and generates the analog feedback signal. At least the first ADC is a multi-bit Successive Approximation Register ADC.

Abstract: An analog-to-digital converter has a switched capacitor comprising a capacitor to perform charging and discharging by switching a switch, the switched capacitor varying a charge amount of the capacitor in accordance with a frequency of an oscillation signal in accordance with a differential signal between an input signal and a feedback signal, capacitance of the capacitor, and a predetermined bias voltage, a feedback signal generator to generate the feedback signal based on an output signal of the switched capacitor, and a digital converter to generate a digital signal by digital conversion of the input signal based on the oscillation signal.

Abstract: A capacitive successive approximation analog-to-digital converter is provided, where the capacitive successive approximation analog-to-digital converter includes a first capacitor array including N first capacitors; a second capacitor array including N second capacitors; a voltage generation circuit configured to generate a common mode voltage, a reference voltage, a first voltage and a second voltage; a first switch, a second switch, N third switches and N fourth switches; a comparator including a first input end, a second input end and an output end, where upper plates of the N first capacitors are connected to the first input end and upper plates of the N second capacitors are connected to the second input end; and a successive approximation logic controller connected to the output end of the comparator. The capacitive successive approximation analog-to-digital converter in the above technical solution can use 2N capacitors to implement outputting an N-bit binary code.

Abstract: The present invention provides an antenna miniaturized topology that is based on the implementation of a conductive loading on a quadrifilar helix antenna. This may be achieved by connecting the tip of the four helical arms to end members which may be circular planar conductors. The miniaturization of the antenna may be further enhanced by incorporating a dielectric material in the space between the four arms.

Abstract: An aerial device can be configured to fly above a route during movement of a vehicle along the route, such as for purposes of capturing image data of the route. The aerial device may include a microstrip antenna. The antenna includes a radiating patch layer, an aperture layer, a first insulator layer, a feed line, and a second insulator layer, all of which are parallel to and stacked on top of one another. The aperture layer is conductive and defines an aperture. The first insulator layer is sandwiched between the radiating patch layer and the aperture layer; thereby, the radiating patch layer and the aperture layer are spaced apart from one another by at least a thickness of the first insulator layer. The first insulator layer has a low dielectric constant. The second insulator layer is sandwiched between the aperture layer and the feed line.

Abstract: An apparatus is provided which comprises: a thermal sensor comprising one or more n-type devices or p-type devices that suffer from subthreshold factor variation, wherein the thermal sensor is to generate an output digital code representing a temperature; and a calibration circuitry coupled to the thermal sensor, wherein the calibration circuitry is to trim the effects of subthreshold factor variation from the output digital code.

Abstract: An information processing device includes: an apparatus main body; and a display mechanism that is provided to be displaceable with respect to the apparatus main body, is provided with an antenna used to perform communication with a mobile terminal, and is configured to display information. The apparatus main body is not located in a place where the display mechanism extends upwards and downwards the display mechanism in a state in which the display mechanism is displaced with respect to the apparatus main body.

Abstract: An example sigma delta modulator (SDM) circuit includes a floor circuit, a subtractor having a first input coupled an input of the floor circuit and a second input coupled to an output of the floor circuit, and a multi-stage noise shaping (MASH) converter having a programmable order. The MASH converter includes an input coupled to an output of the subtractor. The SDM further includes a programmable delay circuit having an input coupled to the output of the floor circuit, and an adder having a first input coupled to an output of the MASH converter and a second input coupled to an output of the programmable delay circuit.

Abstract: A successive approximation register analog-to-digital converter with improved kick-back linearization includes a signal input terminal, a capacitive digital-to-analog converter, a first switch, and a second switch. The signal input terminal is configured to receive a signal to be digitized. The capacitive digital-to-analog converter includes a first capacitor array, a second capacitor array, and a coupling capacitor. The first capacitor array includes a plurality of capacitors. The second capacitor array includes a plurality of capacitors. The coupling capacitor connects the first capacitor array to the second capacitor array. The first switch is configured to switchably connect a bottom plate of each of the capacitors of the first capacitor array to the signal input terminal. The second switch is configured to conduct a voltage on the bottom plate of the coupling capacitor to the signal input terminal.

Abstract: The proposed retro-directive quasi-optical system includes at least a lens set and a pixel array. The lens set is positioned on one side of the pixel array and the lens set instantly establishes retro-directive space channels between the pixels in the pixel array and the object(s) distributed in the accessible space defined by the lens set through infinite or finite conjugation. In the pixel array, a number of pixels are arranged as an array and each pixel is composed of at least one pair of transmitter antenna and receiver antenna. To guarantee that the electromagnetic waves transmitted from a pixel into the accessible space may be reflected back to the receiver of the same pixel, the size of each pixel is not larger than the point-spread spot size defined by the lens set, wherein the point-spread spot size can be contributed either from lens diffraction or aberration.