Abstract: Digit validation check control for execution of an instruction. A process obtains an instruction to perform operation(s) using input value(s). The instruction includes a no validation indicator for controlling whether digit validation check control is enabled for execution of the instruction. The process executes the instruction, including determining, based on the no validation indicator, whether digit validation check control is enabled for execution of the instruction, and performing processing based on the determining. Based on the no validation indicator being set to a defined value, digit validation check control is enabled and the processing includes forcing a digit check error indicator output by the executing to indicate no digit check error with respect to the at least one input value.

Abstract: A processor includes an execution unit and a processing logic operatively coupled to the execution unit, the processing logic to: enter a first execution state and transition to a second execution state responsive to executing a control transfer instruction. Responsive to executing a target instruction of the control transfer instruction, the processing logic further transitions to the first execution state responsive to the target instruction being a control transfer termination instruction of a mode identical to a mode of the processing logic following the execution of the control transfer instruction; and raises an execution exception responsive to the target instruction being a control transfer termination instruction of a mode different than the mode of the processing logic following the execution of the control transfer instruction.

Abstract: Embodiments described herein provide techniques to manage drivers in a user space in a data processing system. One embodiment provides a data processing system configured perform operations, comprising discovering a hardware device communicatively coupled to the communication bus, launching a user space driver daemon, establishing an inter-process communication (IPC) link between a first proxy interface for the user space driver daemon and a second proxy interface for a server process in a kernel space, receiving, at the first proxy interface, an access right to enable access to a memory buffer in the kernel space, and relaying an access request for the memory buffer from the user space driver daemon via a third-party proxy interface to enable the user space driver daemon to access the memory buffer, the access request based on the access right.

Abstract: Techniques and mechanisms described herein include a signal processor implemented as an overlay on a field-programmable gate array (FPGA) device that utilizes special purpose, hardened intellectual property (IP) modules such as memory blocks and digital signal processing (DSP) cores. A Processing Element (PE) is built from one or more DSP cores connected to additional logic. Interconnected as an array, the PEs may operate in a computational model such as Single Instruction-Multiple Thread (SIMT). A software hierarchy is described that transforms the SIMT array into an effective signal processor.

Abstract: A data storage device includes a case and a connector housed within the case. The connector includes a first connection interface having a plurality of connection fingers and a second connection interface having a plurality of springs. The case is positionable within a data storage device port such that the data storage device is completely disposed within the data storage device port when used.

Abstract: An aspect includes memory access optimization for an I/O adapter in a processor complex. A memory block distance is determined between the I/O adapter and a memory block location in the processor complex and determining one or more memory movement type criteria between the I/O adapter and the memory block location based on the memory block distance. A memory movement operation type is selected based on a memory movement process parameter and the one or more memory movement type criteria. A memory movement process is initiated between the I/O adapter and the memory block location using the memory movement operation type.

Abstract: In one embodiment, a cache coherent system includes one or more agents (e.g. coherent agents) that may cache data used by the system. The system may include a point of coherency in a memory controller in the system, and thus the agents may transmit read requests to the memory controller to coherently read data. The point of coherency may determine if the data is cached in another agent, and may transmit a copy back request to the other agent if the other agent has modified the data. The system may include an interconnect between the agents and the memory controller. At a point on the interconnect at which traffic from the agents converges, a copy back response may be converted to a fill for the requesting agent.

Abstract: A method and apparatus are provided to receive a voltage at a first value at a voltage reducing adaptor, ascertain a voltage supply requirement for the memory arrangement to obtain and ascertained voltage supply requirement, reduce the voltage from the first value to the ascertained voltage supply requirement within the adaptor and supply the voltage at the ascertained voltage supply requirement to the memory arrangement.

Abstract: Systems and methods are disclosed for macro-op fusion. Sequences of macro-ops that include a control-flow instruction are fused into single micro-ops for execution. The fused micro-ops may avoid the use of control-flow instructions, which may improve performance. A fusion predictor may be used to facilitate macro-op fusion.

Abstract: A transmission interface communicating method used in a display device that includes the steps outlined below is provided. A first status update signal is received from a host device to turn a hot plug detect (HPD) status of the display device to a high status. A HPD signal having a low status is transmitted to the host device in response to the first status update signal. A configuration signal is received from the host device. A configuration acknowledgement signal is transmitted to the host device in response to the configuration signal. The HPD signal having the high status is actively transmitted to the host device.

Abstract: A processor includes a load/store unit that includes one or more load pipelines and one or more store pipelines. Load operations may be issued into the load pipelines out of order with respect to older store operations. If a load operation is executed out or order with an older store operation that writes one or more bytes read by the load operation, and if the store operation is issued shortly after the load operation, such that the load operation is still in the load pipeline when the store operation is issued, some cases of flushing may be converted to replays by detecting the ordering violation while the load operation is still in the load pipeline.

Abstract: A reconfigurable computing appliance includes a number of computing tiles. Each computing tile includes a reconfigurable processing element and a network fabric interface device configured to communicate over a network fabric. The reconfigurable processing element operates on data received from an I/O input interface and/or data received via the network fabric interface device.

Abstract: Provided is a patch panel, comprising: a circuit board; and an SFP, SFP+, or QSFP+ connector connected to a plurality of radio frequency coaxial (RF coaxial) connections via conductive traces of the circuit board, the RF coaxial connections configured to extend functionality of the SFP, SFP+, or QSFP+ socket of a computing device coupled to the patch panel from a rear end of the computing device to a front end of the computing device.

Abstract: Methods, systems and computer program products for heuristically invalidating non-useful entries in an array are provided. Aspects include receiving an instruction that is associated with an operand store compare (OSC) prediction for at least one of a store function and a load function. The OSC prediction is stored in an entry of an OSC history table (OHT). Aspects also include executing the instruction. Responsive to determining, based on the execution of the instruction, that data forwarding did not occur, aspects include incrementing a useless OSC prediction counter. Responsive to determining that the useless OSC prediction counter is equal to a predetermined value, aspects also include invalidating the entry of the OHT associated with the instruction.

Abstract: An arithmetic processing apparatus includes a shift register configured to store a plurality of transactions each having one or more destinations; and a processor coupled to the shift register and configured to: select a first transaction among the transactions stored in the shift register based on a state of a destination of each of the transactions, determine whether or not the first transaction is issuable, select a second transaction based on destinations of the first transaction when it is determined that the first transaction is not issuable, issue the first transaction when it is determined that the first transaction is issuable, and issue the second transaction when it is determined that the first transaction is not issuable.

Abstract: Disclosed embodiments relate to systems and methods for performing instructions to transform matrices into a row-interleaved format. In one example, a processor includes fetch and decode circuitry to fetch and decode an instruction having fields to specify an opcode and locations of source and destination matrices, wherein the opcode indicates that the processor is to transform the specified source matrix into the specified destination matrix having the row-interleaved format; and execution circuitry to respond to the decoded instruction by transforming the specified source matrix into the specified RowInt-formatted destination matrix by interleaving J elements of each J-element sub-column of the specified source matrix in either row-major or column-major order into a K-wide submatrix of the specified destination matrix, the K-wide submatrix having K columns and enough rows to hold the J elements.

Abstract: A method for detecting and identifying modules of a bus system is provided. The bus system includes a control unit, a bus starting from the control unit, and a plurality of modules connected to the bus. The method includes providing a current sink associated with each of the one or more modules. The current sink includes a transistor. The method includes providing a hall sensor associated with each of the one or more modules. The hall sensor detects a current on a low-side data line of the bus. For each one of the one or more modules: when the hall sensor detects a current on the low-side data line, the method includes maintaining a closed position of the transistor; and when the hall sensor fails to detect a current on the low-side data line, the method includes opening the transistor such that current does not flow to the module.

Abstract: A reconfigurable processing circuit and system are provided. The system allows a user to program machine-level instructions in order to reconfigure the way the circuit behaves, including by adding new operations. The system can include a profile access content-addressable memory (CAM) configured to receive an execution step value from a step counter. The execution step value can be incremented and/or reset by a step management logic. The profile access CAM can select an entry of a profile table based on an opcode and the execution step value, and the processing engine can execute microcode based on the selected entry of the profile table. The profile access CAM can translate the opcode to an internal short instruction identifier in order to select the entry of the profile table. The system can further include an instruction decoding module configured to merge multiple instruction fields into a single effective instruction field.

Abstract: A processor core and methods for managing the processor core. The processor core comprises of a plurality of lanes, each lane comprising a copy of a register file logically shared across the plurality lanes and a plurality of functional units, at least two of the functional units sharing a common cache and a common control unit, where the common control unit concurrently dispatches multiple consecutive instances of an instruction corresponding to multiple successive instances of an inner loop to the plurality of functional units of at least a proper subset of the plurality of lanes; and one or more registers of each copy of the register file, each register being configurable to write a data result from at least one of the functional units to a register in a lane-local mode, a lane-forward mode, and a normal mode.

Abstract: An arithmetic processing device includes: a pipeline circuit including an instruction fetch circuit, an instruction decoder that performs a first branch misprediction determination for a branch instruction, and issues the instructions in-order, a branch instruction processing circuit which performs a second branch misprediction determination for the branch instruction; and a commit processing circuit that executes a commit processing of the processed instructions in-order.