Abstract: A single-wire two-way communication circuit includes two chips and a data transmission line coupled between the two chips. Each chip includes a random access memory, a data control module, a data line control module, and a data line monitoring module. The random access memory stores data. The data control module obtains data of a first address from the random access memory and stores data of a second address received from the other chip into a second address of the random access memory. The data line control module sends the obtained data of the first address to the other chip through the data transmission line to perform a write operation. The data line monitoring module receives the data of the second address sent by the other chip through the data transmission line to perform a read operation.

Abstract: A representative reconfigurable processing circuit and a reconfigurable arithmetic circuit are disclosed, each of which may include input reordering queues; a multiplier shifter and combiner network coupled to the input reordering queues; an accumulator circuit; and a control logic circuit, along with a processor and various interconnection networks. A representative reconfigurable arithmetic circuit has a plurality of operating modes, such as floating point and integer arithmetic modes, logical manipulation modes, Boolean logic, shift, rotate, conditional operations, and format conversion, and is configurable for a wide variety of multiplication modes. Dedicated routing connecting multiplier adder trees allows multiple reconfigurable arithmetic circuits to be reconfigurably combined, in pair or quad configurations, for larger adders, complex multiplies and general sum of products use, for example.

Abstract: In an example, an apparatus comprises a plurality of execution units, and logic, at least partially including hardware logic, to assemble a general register file (GRF) message and hold the GRF message in storage in a data port until all data for the GRF message is received. Other embodiments are also disclosed and claimed.

Abstract: A circuit provides for processing and routing peer-to-peer (P2P) traffic. A bus request queue store a data request received from a first peer device. A decoder compares an address portion of the data request against an address map to determine whether the data request is directed to either a second peer device or a local memory. A bus interface unit, in response to the data request being directed to the second peer device, 1) generates a memory access request from the bus request and 2) transmits the memory access request toward the second peer device via a bus. A memory controller, in response to the data request being directed to a local memory, accesses the local memory to perform a memory access operation based on the data request.

Abstract: A processor for sparse matrix calculation can include an on-chip memory, a cache, a gather/scatter engine and a core. The on-chip memory can be configured to store a first matrix or vector, and the cache can be configured to store a compressed sparse second matrix data structure. The compressed sparse second matrix data structure can include: a value array including non-zero element values of the sparse second matrix, where each entry includes a given number of element values; and a column index array where each entry includes the given number of offsets matching the value array. The gather/scatter engine can be configured to gather element values of the first matrix or vector using the column index array of the sparse second matrix. In a horizontal implementation, the gather/scatter engine can be configured to gather sets of element values from different sub-banks within a same row based on the column index array of the sparse matrix.

Abstract: According to one embodiment, a semiconductor memory device includes a first string including a first memory cell transistor and a second memory cell transistor which are coupled in series, a first switch element, a first latch circuit coupled in series between a first end of the first string and a first end of the first switch element, and a second switch element and a third switch element coupled in parallel between a second end of the first switch element and a data bus.

Abstract: A Baseboard Management Controller (BMC) (125) that may configure itself is disclosed. The BMC (125) may include an access logic (415) to determine a configuration of a chassis (105) that includes the BMC (125). The BMC (125) may also include a built-in self-configuration logic (420) to configure the BMC (125) responsive to the configuration of the chassis (105). The BMC (125) may self-configure without using any BIOS, device drivers, or operating systems.

Abstract: A toner container installable in an image forming device having a controller according to one example embodiment includes a housing having a reservoir for storing toner. A chip is positioned on the housing and configured to, after sending a first busy response to the controller of the image forming device, receive a second write command from the controller of the image forming device that is abbreviated relative to a first write command received from the controller of the image forming device and that requests the chip to send a response to the first write command. The chip is further configured to send a response to the first write command to the controller of the image forming device if upon receiving a read command corresponding to the second write command the chip has completed processing the first write command.

Abstract: A multi-package system includes a first semiconductor package and a second semiconductor package. The first semiconductor package includes a first die and a second die. The second semiconductor package includes a third die. A first processing circuit of the first die communicates with a second processing circuit of the second die through a first configurable input/output (IO) interface circuit of the first die and a third configurable IO interface circuit of the second die that are configured to perform single-ended intra-package communication. The first processing circuit of the first die communicates with a third processing circuit of the third die through a second configurable IO interface circuit of the first die and a fourth configurable IO interface circuit of the third die that are configured to perform differential inter-package communication. The first configurable IO interface circuit and the second configurable IO interface circuit have a same circuit design.

Abstract: A processor comprises a trusted execution environment and a non-trusted execution environment. The processor further comprises a common resource accessible in both the trusted execution environment and the non-trusted execution environment and an instruction processing device including circuitry configured to fetch an instruction for decoding and execute the decoded instruction. The instruction processing device includes circuitry further configured to determine consistency between a current execution environment of the processor and a resource status in response to a result from instruction decoding indicating that instruction involves access to the common resource, and load content corresponding to the current execution environment into the common resource in response to a determination that the current execution environment is inconsistent with the resource status, wherein the resource status indicates an execution environment corresponding to content in the common resource.

Abstract: Aspects for vector operations in neural network are described herein. The aspects may include a vector caching unit configured to store a first vector and a second vector, wherein the first vector includes one or more first elements and the second vector includes one or more second elements. The aspects may further include one or more adders and a combiner. The one or more adders may be configured to respectively add each of the first elements to a corresponding one of the second elements to generate one or more addition results. The combiner may be configured to combine a combiner configured to combine the one or more addition results into an output vector.

Abstract: A processor core, a processor, an apparatus, and an instruction processing method are disclosed. The processor core includes: an instruction fetch unit, where the instruction fetch unit includes a speculative execution predictor and the speculative execution predictor compares a program counter of a memory access instruction with a table entry stored in the speculative execution predictor and marks the memory access instruction; a scheduler unit adapted to adjust a send order of marked memory access instructions and send the marked memory access instructions according to the send order; an execution unit adapted to execute the memory access instructions according to the send order. In the instruction fetch unit, a memory access instruction is marked according to a speculative execution prediction result. In the scheduler unit, a send order of memory access instructions is determined according to the marked memory access instruction and the memory access instructions are sent.

Abstract: An apparatus comprising: processing circuitry to process threads of data processing; and transactional memory support circuitry to support execution of a transaction within a thread processed by the processing circuitry. In response to a transactional compare-and-discard instruction executed within a given transaction, specifying a target address and a compare value, the processing circuitry loads a target data value from a memory location corresponding to the target address; sets at least one condition status indication depending on a result of comparing the target data value and the compare value; and discards the target data value without adding the target address to a working set of addresses tracked for the given transaction. This is useful for enabling thread level speculation to be implemented on a transactional memory architecture.

Abstract: Aspects for vector operations in neural network are described herein. The aspects may include a vector caching unit configured to store a vector, wherein the vector includes one or more elements. The aspects may further include a computation module that includes one or more comparers configured to compare the one or more elements to generate an output result that satisfies a predetermined condition included in an instruction.

Abstract: Methods and apparatus for improved send/receive operations in network interface fabrics. In one exemplary embodiment, mechanisms and protocols for enhanced inter-process (and inter-endpoint) communication, including within very large scale topologies involving e.g., hundreds or even thousands of nodes or endpoints, such as a large-scale high-performance compute or network fabric, are described. In one implementation, the methods and apparatus avoid frequent kernel transitions (and the performance penalties associated therewith) associated with prior approaches through use of UMCs (user message contexts) are created, which contain TX and RX queues that can be read and written directly from user space. A KMC (kernel message context) is also used, in which TX queues are written from the kernel such that access can be arbitrated between unrelated processes. These functions allow for, among other things, significant portions of the foregoing kernel accesses to be obviated.

Abstract: A method and apparatus are provided to receive a voltage at a first value at a voltage reducing adaptor, ascertain a voltage supply requirement for the memory arrangement to obtain and ascertained voltage supply requirement, reduce the voltage from the first value to the ascertained voltage supply requirement within the adaptor and supply the voltage at the ascertained voltage supply requirement to the memory arrangement.

Abstract: A data transmission system includes a first memory, a second memory, a third memory; and a memory controller. The memory controller includes a first channel control module and a second channel control module. The first channel control module is coupled to the first memory and the second memory. The first channel control module transmits a first set of data between the first memory and the second memory, and transmits a switch signal after the first set of data is transmitted. The second channel control module is coupled to the first channel control module, the first memory, and the third memory. The second channel control module transmits a second set of data between the first memory and the third memory after receiving the switch signal.

Abstract: A processing device is configured to communicate over a network with a storage system comprising a plurality of storage devices. The device comprises a multi-path input-output (MPIO) driver configured to control delivery of input-output (IO) operations from the device to the storage system over selected ones of a plurality of paths through the network. The paths are associated with respective initiator-target pairs, and each of a plurality of targets of the initiator-target pairs comprises a corresponding port of the storage system. The MPIO driver is further configured to create a plurality of IO operation threads, to use a given IO operation thread to retrieve a given IO operation from an IO queue, to attempt to perform the given IO operation on a given target of the plurality of targets, and to return the given IO operation to the IO queue upon a failure to perform the given IO operation.

Abstract: Disclosed embodiments relate to systems and methods for performing instructions to transform matrices into a row-interleaved format. In one example, a processor includes fetch and decode circuitry to fetch and decode an instruction having fields to specify an opcode and locations of source and destination matrices, wherein the opcode indicates that the processor is to transform the specified source matrix into the specified destination matrix having the row-interleaved format; and execution circuitry to respond to the decoded instruction by transforming the specified source matrix into the specified RowInt-formatted destination matrix by interleaving J elements of each J-element sub-column of the specified source matrix in either row-major or column-major order into a K-wide submatrix of the specified destination matrix, the K-wide submatrix having K columns and enough rows to hold the J elements.

Abstract: A data processing apparatus is specified, having multiple processor devices (4), multiple interface devices (5), to which external devices (E) are respectively connectable, and having connections (8, 10) between the interface devices (5) and the processor devices (4), via which data are transportable between the interface devices (5) and the processor devices (4). In the connections (8, 10), there is provision for at least one data management device (20) for handling data flows between the interface devices (5) and the processor devices (4). The data management device (20) is in the form of a hardware component.