Patents Examined by Igwe U. Anya
  • Patent number: 11921419
    Abstract: A method of fabricating a semiconductor device includes performing an optical proximity correction (OPC) operation on a design pattern of a layout, and forming a photoresist pattern on a substrate, using a photomask which is manufactured with the layout corrected by the OPC operation. The OPC operation includes generating a target pattern based on the design pattern, performing a first OPC operation, based on the target pattern, to generate a first correction pattern, measuring a target error by comparing a first simulation image of the first correction pattern with the target pattern, generating a retarget pattern from the target pattern, based on the target error, and performing a second OPC operation, based on the retarget pattern, to generate a second correction pattern.
    Type: Grant
    Filed: July 22, 2021
    Date of Patent: March 5, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sooyong Lee, Bong-Soo Kang
  • Patent number: 11917854
    Abstract: A display panel, a display device, and a driving method thereof are provided. A light-reflecting layer is disposed under a light-emitting layer of the display panel. When the display panel is under strong light, the light-emitting layer does not work, and the light-reflecting layer reflects natural light to achieve a full-color display. When the display panel is in low light or darkness, the light-emitting layer works, and the light-reflecting layer reflects the light emitted by the light-emitting layer to reduce a working intensity of the light-emitting layer and achieves the full-color display, thereby improving service life and visual effect of organic light emitting diodes (OLEDs).
    Type: Grant
    Filed: April 7, 2020
    Date of Patent: February 27, 2024
    Assignee: Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
    Inventor: Xian Li
  • Patent number: 11917906
    Abstract: The invention relates to compounds that can be used in an organic electronic device as an active compound, in particular for use in electronic devices. The invention further relates to a process for preparing the compounds according to the invention, and to electronic devices comprising the same.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: February 27, 2024
    Assignee: Merck Patent GmbH
    Inventor: Philipp Stoessel
  • Patent number: 11917860
    Abstract: A method of manufacturing a display panel includes fabricating a display portion on a glass substrate; forming a barrier layer on the glass substrate outside the display portion; forming an encapsulation film on the barrier layer and the display portion; and obtaining a panel area by removing the barrier layer and the encapsulation film outside a predetermined limited area on the glass substrate. The predetermined limited area corresponds to the display portion.
    Type: Grant
    Filed: November 21, 2019
    Date of Patent: February 27, 2024
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Lei Zhao, Gaozhen Wang
  • Patent number: 11916137
    Abstract: A semiconductor device may include: a drift region of a first conductivity type; a base region of a second conductivity type arranged on the drift region; an emitter region of the first conductivity type arranged on the base region; a field stop region of the first conductivity type arranged in contact with the drift region; a collector region of the second conductivity type in contact with the field stop region; a main gate electrode electrically insulated from the base region and the collector region; a control gate electrode electrically insulated from the base region and the collector region; a gate pad on the drift region; a first resistor electrically connected between the gate pad and the main gate electrode; and a second resistor electrically connected between the gate pad and the control gate electrode. A resistance value of the first resistor may be greater than the second resistor thereof.
    Type: Grant
    Filed: October 27, 2021
    Date of Patent: February 27, 2024
    Assignee: SANKEN ELECTRIC CO., LTD.
    Inventor: Katsuyuki Torii
  • Patent number: 11908922
    Abstract: A semiconductor structure includes a substrate, a first epitaxial layer, a second epitaxial layer, and a transistor. The substrate includes a first pyramid protrusion, a second pyramid protrusion, a third pyramid protrusion, and a fourth pyramid protrusion. The first and second pyramid protrusions are arranged along a first direction, the second and fourth pyramid protrusions are arranged along the first direction, and the first and third pyramid protrusions are arranged along a second direction crossing the first direction. The first epitaxial layer is over the substrate and in contact with the first, second, third, and fourth pyramid protrusions. The second epitaxial layer is over the first epitaxial layer. The transistor is over the second epitaxial layer.
    Type: Grant
    Filed: October 26, 2020
    Date of Patent: February 20, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Carlos H. Diaz, Mark Van Dal, Martin Christopher Holland
  • Patent number: 11908925
    Abstract: A semiconductor device includes a first electrode, a second electrode, a first semiconductor region, a second semiconductor region, a third semiconductor region, a fourth semiconductor region, a fifth semiconductor region, a first gate electrode, and a second gate electrode. The first gate electrode faces the second semiconductor region via a first insulating film. The second gate electrode faces the second semiconductor region via a second insulating film and faces the second electrode via a third insulating film contacting the second insulating film. The fifth semiconductor region includes a boundary portion that electrically contacts the second electrode. A distance between an upper surface of the fourth semiconductor region and the first electrode is greater than a distance between the boundary portion and the first electrode.
    Type: Grant
    Filed: September 7, 2021
    Date of Patent: February 20, 2024
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Yoko Iwakaji, Tomoko Matsudai, Hiroko Itokazu, Keiko Kawamura
  • Patent number: 11894451
    Abstract: A semiconductor device includes first and second source/drain regions, a core channel region, a barrier layer, a shell, and a gate stack. The core channel region is between the first and second source/drain regions and is doped with first dopants. The barrier layer is between the core channel region and the second source/drain region and is doped with second dopants. The shell is over the core channel region and the barrier layer. The gate stack is over the shell.
    Type: Grant
    Filed: May 28, 2021
    Date of Patent: February 6, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Aryan Afzalian
  • Patent number: 11888032
    Abstract: A method of producing a silicon carbide (SiC) device includes: forming a stripe-shaped trench gate structure that extends from a first surface of a SiC body into the SiC body, the gate structure having a gate length along a lateral first direction, a bottom surface and a first gate sidewall of the gate structure being connected via a first bottom edge of the gate structure; forming at least one source region of a first conductivity type; and forming a shielding region of a second conductivity type in contact with the first bottom edge of the gate structure across at least 20% of the gate length. Forming the shielding region includes: forming a deep shielding portion; and forming a top shielding portion between the first surface and the deep shielding portion, the top shielding portion being in contact with the first bottom edge.
    Type: Grant
    Filed: December 2, 2022
    Date of Patent: January 30, 2024
    Assignee: Infineon Technologies AG
    Inventors: Caspar Leendertz, Thomas Basler, Paul Ellinghaus, Rudolf Elpelt, Michael Hell, Jens Peter Konrath, Shiqin Niu, Dethard Peters, Konrad Schraml, Bernd Leonhard Zippelius
  • Patent number: 11888092
    Abstract: A display device includes a first electrode, a second electrode spaced apart from the first electrode and facing the first electrode, a first insulating layer disposed to at least partially cover the first electrode and the second electrode, a second insulating layer disposed on at least a part of the first insulating layer, and a light-emitting element disposed on the second insulating layer between the first electrode and the second electrode, wherein at least a part of a lower surface of the light-emitting element is chemically bonded to the second insulating layer.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: January 30, 2024
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jae Hoon Jung, Won Ho Lee, Hyun Deok Im
  • Patent number: 11876127
    Abstract: An IGBT capable of handling high-speed switching while reducing a leakage current of a semiconductor device including the IGBT is provided. The semiconductor device according to one embodiment includes an IGBT including a p-type collector layer on a back surface of a silicon substrate and a dislocation suppressing layer for forming a hetero junction with silicon in the p-type collector layer. The dislocation suppressing layer includes a silicon germanium (SiGe) layer.
    Type: Grant
    Filed: August 18, 2021
    Date of Patent: January 16, 2024
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Tomohiro Imai, Yoshito Nakazawa, Katsumi Eikyu
  • Patent number: 11876133
    Abstract: A silicon carbide device includes a transistor cell with a source region and a gate electrode. The source region is formed in a silicon carbide body and has a first conductivity type. A first low-resistive ohmic path electrically connects the source region and a doped region of a second conductivity type. The doped region and a floating well of the first conductivity type form a pn junction. A first clamp region having the second conductivity type extends into the floating well. A second low-resistive ohmic path electrically connects the first clamp region and the gate electrode.
    Type: Grant
    Filed: September 29, 2021
    Date of Patent: January 16, 2024
    Assignee: Infineon Technologies AG
    Inventors: Joachim Weyers, Franz Hirler, Wolfgang Jantscher, David Kammerlander, Ralf Siemieniec
  • Patent number: 11869940
    Abstract: A feeder design is manufactured as a structure in a SiC semiconductor material comprising at least two p-type grids in an n-type SiC material (3), comprising at least one epitaxially grown p-type region, wherein an Ohmic contact is applied on the at least one epitaxially grown p-type region, wherein an epitaxially grown n-type layer is applied on at least a part of the at least two p-type grids and the n-type SiC material (3) wherein the at least two p-type grids (4, 5) are applied in at least a first and a second regions at least close to the at least first and second corners respectively and that there is a region in the n-type SiC material (3) between the first and a second regions without any grids.
    Type: Grant
    Filed: January 5, 2023
    Date of Patent: January 9, 2024
    Assignee: II-VI DELAWARE, INC.
    Inventors: Hossein Elahipanah, Nicolas Thierry-Jebali, Adolf Schoner, Sergey Reshanov
  • Patent number: 11871615
    Abstract: A display device includes: a base substrate; a TFT layer including a plurality of pixel circuits arranged; and a light-emitting element layer. Each of the plurality of pixel circuits includes: a TFT including a semiconductor layer, a gate insulating film, and a gate electrode; and a capacitor including the gate electrode, a first inorganic insulating film, and a capacitive electrode. The capacitive electrode extends all around a perimeter of the gate electrode and extends to an outside of the perimeter. An angle formed between an upper surface of the base substrate and at least a part of an end surface in a circumferential direction of the gate electrode not overlapping the semiconductor layer in the plan view is greater than an angle formed between the upper surface of the base substrate and an end surface of the gate electrode overlapping the semiconductor layer in the plan view.
    Type: Grant
    Filed: December 7, 2018
    Date of Patent: January 9, 2024
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Takao Saitoh, Masahiko Miwa, Yohsuke Kanzaki, Masaki Yamanaka, Yi Sun
  • Patent number: 11869960
    Abstract: Provided is a semiconductor device, comprising a semiconductor substrate; and an emitter electrode provided above an upper surface of the semiconductor substrate; wherein the semiconductor substrate has: a first conductive type drift region; a second conductive type base region provided between the drift region and the upper surface of the semiconductor substrate; a second conductive type contact region with a higher doping concentration than the base region, which is provided between the base region and the upper surface of the semiconductor substrate; a trench contact of a conductive material provided to connect to the emitter electrode and penetrate the contact region; and a second conductive type high-concentration plug region with a higher doping concentration than the contact region, which is provided in contact with a bottom portion of the trench contact.
    Type: Grant
    Filed: March 24, 2021
    Date of Patent: January 9, 2024
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Soichi Yoshida
  • Patent number: 11868847
    Abstract: A method of reducing stray coupling in a qubit array, includes turning ON a first coupler between a first qubit and second qubit of the qubit array by providing a pulse having a first amplitude to the first coupler. A stray coupling between the first coupler and a spectator qubit is reduced by turning ON a second coupler coupled to the spectator qubit, by providing a compensation pulse having a second amplitude, to the second coupler, based on the pulse having the first amplitude.
    Type: Grant
    Filed: March 16, 2021
    Date of Patent: January 9, 2024
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jiri Stehlik, David Zajac
  • Patent number: 11864397
    Abstract: The present application provides a display panel and a display device. The display panel includes a first wiring layer connected between a first pixel driving circuit and a first light-emitting device; a signal wiring layer electrically connected to the first pixel driving circuit and partially overlapping the first wiring layer; and a capacitive barrier layer disposed between the first wiring layer and the signal wiring layer and including at least one organic insulating layer, so as to improve the display effect of the display light-transmitting area through the capacitive barrier layer.
    Type: Grant
    Filed: November 19, 2020
    Date of Patent: January 2, 2024
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Jia Zhang, Feifei Peng
  • Patent number: 11859313
    Abstract: An 8-inch SiC single crystal substrate of an embodiment has a diameter in a range of 195 mm to 205 mm, a thickness in a range of 300 ?m to 650 ?m, a SORI of 50 ?m or less, and an in-plane variation of the thickness of the substrate, which is the difference between the maximum and minimum substrate thickness at the center of the substrate and four points on the circumference of a circle having a radius half the radius of the substrate, is 1.5 ?m or less.
    Type: Grant
    Filed: May 31, 2023
    Date of Patent: January 2, 2024
    Assignee: Resonac Corporation
    Inventor: Tomohiro Shonai
  • Patent number: 11851596
    Abstract: A lighting device is specified. The lighting device comprises a phosphor having the general molecular formula (MA)a(MB)b(MC)c(MD)d(TA)e(TB)f(TC)g(TD)h(TE)i(TF)j(XA)k(XB)l(XC)m(XD)n:E. In this case, MA is selected from a group of monovalent metals, MB is selected from a group of divalent metals, MC is selected from a group of trivalent metals, MD is selected from a group of tetravalent metals, TA is selected from a group of monovalent metals, TB is selected from a group of divalent metals, TC is selected from a group of trivalent metals, TD is selected from a group of tetravalent metals, TE is selected from a group of pentavalent elements, TF is selected from a group of hexavalent elements, XA is selected from a group of elements which comprises halogens, XB is selected from a group of elements which comprises O, S and combinations thereof, XC=N and XD=C and E=Eu, Ce, Yb and/or Mn. The following furthermore hold true: a+b+c+d=t; e+f+g+h+i+j=u; k+l+m+n=v; a+2b+3c+4d+e+2f+3g+4h+5i+6j?k?2l?3m?4n=w; 0.8?t?1; ?3.
    Type: Grant
    Filed: June 10, 2022
    Date of Patent: December 26, 2023
    Assignee: OSRAM OLED GmbH
    Inventors: Markus Seibald, Simon Peschke, Gregor Hoerder, Gina Maya Achrainer, Klaus Wurst, Dominik Baumann, Tim Fiedler, Stefan Lange, Hubert Huppertz, Daniel Dutzler, Thorsten Schroeder, Daniel Bichler, Gudrun Plundrich
  • Patent number: 11848406
    Abstract: A radiation-emitting semiconductor device (1) is specified, comprising a semiconductor body (2) having an active region (20) provided for generating radiation, a carrier (3) on which the semiconductor body is arranged and an optical element (4), wherein the optical element is attached to the semiconductor body by a direct bonding connection. Furthermore, a method for producing of radiation-emitting semiconductor devices is specified.
    Type: Grant
    Filed: March 2, 2022
    Date of Patent: December 19, 2023
    Assignee: OSRAM OLED GMBH
    Inventors: Roland Heinrich Enzmann, Hubert Halbritter, Martin Rudolf Behringer