Abstract: A semiconductor device includes a semiconductor layer structure and a gate formed in a gate trench in the semiconductor layer structure. The gate trench has a bottom surface comprising a first portion at a first level and a second portion at a second level, different from the first level. A method of forming a semiconductor device includes providing a semiconductor layer structure, etching a first gate trench into the semiconductor layer structure, etching a second gate trench into the semiconductor layer structure, and performing an ion implantation into a bottom surface of the second gate trench. The second gate trench is deeper than the first gate trench, and at least a portion of the second gate trench is connected to the first gate trench.

Abstract: Provided a semiconductor light detection element including: a semiconductor portion having a front surface including a light reception region that receives incident light and photoelectrically converting the incident light incident on the light reception region; a metal portion provided on the front surface; and a carbon nanotube film provided on the light reception region and formed by depositing a plurality of carbon nanotubes. The carbon nanotube film extends over an upper surface of the metal portion from an upper surface of the light reception region.

Abstract: A semiconductor device includes: a semiconductor chip; and a field effect transistor formed on the semiconductor chip and including a plurality of unit cells, which include at least one first unit cell including a first on-resistance component and a first feedback capacitance component, and at least one second unit cell including a second on-resistance component forming a parallel component with respect to the first on-resistance component and exceeding the first on-resistance component and a second feedback capacitance component forming a parallel component with respect to the first feedback capacitance component and being less than the first feedback capacitance component.

Abstract: A trench-gate power MOSFET with optimized layout, comprising: a substrate; a first semiconductor region formed on the substrate, having a first doping type; mutually separated trench isolation gate structure, formed on the first semiconductor region, the trench isolation gate structure includes an gate oxide layer and a gate electrode; a second semiconductor region and a third semiconductor region formed between any two adjacent structures of mutually separated trench isolation gate structures; and a first shielding region, formed under each of the third semiconductor regions, connecting simultaneously with multiple mutually separated trench isolation structures.

Abstract: A display apparatus includes: a first thin-film transistor (TFT) including a first semiconductor layer including a silicon semiconductor; a second TFT including a second semiconductor layer including an oxide semiconductor; a first shielding layer configured to overlap the first TFT and positioned between a substrate and the first TFT; and a second shielding layer configured to overlap the second TFT and positioned between the substrate and the second TFT.

Abstract: A method of cleaning a wafer comprises: a scrubbing operation comprising treating a target wafer to be cleaned with a brush at a rotation rate of 200 rpm or less to prepare a brush cleaned wafer; and a cleaning operation comprising cleaning the brush cleaned wafer with a cleaning solution to prepare a cleaned bare wafer, wherein the cleaning operation comprises a first cleaning operation and a second cleaning operation sequentially.

Abstract: Semiconductor devices and methods of forming the devices are provided. Semiconductor devices include a semiconductor layer structure comprising a trench in an upper surface thereof, a dielectric layer in a lower portion of the trench, and a gate electrode in the trench and on the dielectric layer opposite the semiconductor layer structure. The trench may include rounded upper corner and a rounded lower corner. A center portion of a top surface of the dielectric layer may be curved, and the dielectric layer may be on opposed sidewalls of the trench. The dielectric layer may include a bottom dielectric layer on a bottom surface of the trench and on lower portions of the sidewalls of the trench and a gate dielectric layer on upper portions of the sidewalls of the trench and on the bottom dielectric layer.

Abstract: Transistors include a pyramid-shaped gate trench defined by a triangular shape or a trapezoidal shape in a channel width plane and a trapezoidal shape in a channel length plane. Side wall portions of the pyramid-shaped gate trench form a channel having a triangular shape or a trapezoidal shape in the channel width plane. Advantageously, such transistors increase transconductance without increasing pixel width. Devices, image sensors, and pixels incorporating such transistors are also provided, in addition to methods of manufacturing the same.

Abstract: According to one aspect of the present disclosure, a semiconductor device includes a substrate; a drift layer of a first conductivity type provided on the substrate; a base layer of a second conductivity type provided above the drift layer on the substrate; a source layer of the first conductivity type provided on an upper surface side of the base layer; a first electrode electrically connected to the source layer; a second electrode provided on the rear surface of the substrate; a gate electrode; a trench gate extending from an upper surface of the substrate to the drift layer; and a first bottom layer of the second conductivity type provided below the trench gate in the drift layer, wherein a first distance between a portion of the first bottom layer where an impurity concentration peaks in a thickness direction and the trench gate is larger than 1 ?m.

Abstract: The height of a solid-state imaging element is further reduced as compared to the related art. A solid-state imaging element that is a wafer-level chip size package, including: an optical sensor chip; a protective layer that is stacked on a light receiving surface of the optical sensor chip; and a rewiring layer that is stacked on a surface opposite to the light receiving surface of the optical sensor chip, in which a connection terminal of the rewiring layer is a copper flat pad without a solder ball, an alloy layer of tin and copper is not formed on a front surface of the flat pad, and a thermal expansion coefficient of the protective layer is substantially balanced with a thermal expansion coefficient of the rewiring layer.

Abstract: A power semiconductor device comprises a semiconductor layer structure having a wide band-gap drift region having a first conductivity type, a gate trench having first and second opposed sidewalls that extend in a first direction in an upper portion of the semiconductor layer structure, first and second well regions having a second conductivity type in the upper portion of the semiconductor layer structure, the first well region comprising part of the first sidewall and the second well region comprising part of the second sidewall. A deep shielding region having the second conductivity type is provided underneath the gate trench, and a plurality of deep shielding connection patterns that have the second conductivity type are provided that electrically connect the deep shielding region to the first and second well regions. The deep shielding connection patterns are spaced apart from each other along the first direction.

Abstract: An electronic device is disclosed. The electronic device includes a conductor, and a conductive oxide material electrically connected to the conductor. The conductive oxide materials is substantially amorphous, and the conductive oxide material includes first and second oxide materials. In addition, the first oxide material is different from the second oxide material. The electronic device also includes a second material, electrically connected to the conductive oxide material.

Abstract: A method including forming a III-V compound layer on a substrate and implanting a main dopant in the III-V compound layer to form source and drain regions. The method further includes implanting a group V species into the source and drain regions. A semiconductor device including a substrate and a III-V compound layer over the substrate. The semiconductor device further includes source and drain regions in the III-V layer, wherein the source and drain regions comprises a first dopants and a second dopant, and the second dopant comprises a group V material.

Abstract: Transistors having nonplanar electron channels in the channel width plane have one or more features that cause the different parts of the nonplanar electron channel to turn on at substantially the same threshold voltage. Advantageously, such transistors have substantially uniform threshold voltage across the nonplanar electron channel. Devices, image sensors, and pixels incorporating such transistors are also provided, in addition to methods of manufacturing the same.

Abstract: A feeder design is manufactured as a structure in a SIC semiconductor material comprising at least two p-type grids in an n-type SiC material (3), comprising at least one epitaxially grown p-type region, wherein an Ohmic contact is applied on the at least one epitaxially grown p-type region, wherein an epitaxially grown n-type layer is applied on at least a part of the at least two p-type grids and the n-type SiC material (3) wherein the at least two p-type grids (4, 5) are applied in at least a first and a second regions at least close to the at least first and second corners respectively and that there is a region in the n-type SiC material (3) between the first and a second regions without any grids.

Abstract: Provided is a semiconductor device comprising an active region and an edge region, the semiconductor device comprising: a drift region of a first conductivity type provided in the semiconductor substrate; a base region of a second conductivity type provided above the drift region; a first collector region of the second conductivity type provided below the drift region in the active region; and a second collector region of the second conductivity type provided below the drift region in the edge region, wherein a doping concentration of the first collector region is higher than a doping concentration of the second collector region, wherein an area of the first collector region is of the same size as an area of the second collector region or larger than the area of the second collector region, in a top plan view.

Abstract: A semiconductor substrate has a transistor region, a diode region, and an outer peripheral region. The transistor region is divided into a plurality of transistor unit cell regions by a plurality of gate electrodes each having a stripe shape, and the diode region is divided into a plurality of diode unit cell regions by the plurality of gate electrodes. Each of the plurality of transistor unit cell regions has a third semiconductor layer of a first conductivity type provided on a first main surface side of the semiconductor substrate, a fourth semiconductor layer of a second conductivity type selectively provided on an upper layer part of the third semiconductor layer, and a fifth semiconductor layer. The fifth semiconductor layer is provided to be in contact with an impurity layer of the first conductivity type provided in the outer peripheral region, or to enter the impurity layer.

Abstract: A vertical power semiconductor device includes a semiconductor body having opposing first and second main surfaces. At least part of a gate trench structure formed at the first main surface extends along a first lateral direction. Body and source regions directly adjoin the gate trench structure. A drift region is arranged between the body region and second main surface. A body contact structure includes first and second body contact sub-regions spaced at a first lateral distance along the first lateral direction. Each body contact sub-region directly adjoins the gate trench structure and has a larger doping concentration than the body region. In a channel region between the body contact sub-regions, the body contact structure has a second lateral distance to the gate trench structure along a second lateral direction perpendicular to the first lateral direction. The first lateral distance is equal to or less than twice the second lateral distance.

Abstract: A semiconductor element includes a semiconductor part, first to third electrodes and a control electrode. The first electrode is provided at a front side of the semiconductor part. The second and third electrodes are provided at a back side of the semiconductor part. The control electrode is provided between the semiconductor part and the first electrode. The semiconductor part includes first and third layers of a first conductivity type and second and fourth layers of a second conductivity type. The first layer is provided between the first and second electrodes and between the first and third electrodes. The first layer is connected to the third electrode at the back side. The second layer is provided between the first layer and the first electrode. The third layer is provided between the second layer and the first electrode. The fourth layer is provided between the second electrode and the first layer.

Abstract: A semiconductor device includes a source/drain diffusion area, a first doped region and a gate. The source/drain diffusion area, defined between a first isolation structure and a second isolation structure, includes a source region, a drain region and a device channel. The first doped region, disposed along a first junction between the device channel and the first isolation structure, is separated from at least one of the source region and the drain region. The first doped region has a dopant concentration higher than that of the device channel. The gate is disposed over the source/drain diffusion area. The first doped region is located within a projected area of the gate onto the source/drain diffusion area, the first isolation structure and the second isolation structure. A length of the first doped region is shorter than a length of the gate in a direction from the source region to the drain region.