Patents Examined by Indranil Chowdhury
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Patent number: 11656958Abstract: Methods, systems, and devices for redundant data bus inversion (DBI) sharing are described. A device may identify a group of channels included in a data bus. The device may determine whether the group of channels satisfies a criterion. Based on the determination, the device may allocate an overhead channel to the group of channels for a set of redundancy operations. Based on the determination, the device may allocate the overhead channel to the group of channels for a set of data bus inversion operations. The device may encode data associated with the group of channels based on the allocation of the overhead channel. The overhead channel may be included in the data bus.Type: GrantFiled: April 29, 2021Date of Patent: May 23, 2023Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Liron Mula, Gil Levy, Itamar Rabenstein
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Patent number: 11650892Abstract: Disclosed is using service-based controllers to manage test agents and performance of multi-agent tests running on a network, a connection-interrupted agent losing connection to a first controller, calling home after the loss, and being connected to a second controller which, after being connected to the agent, accesses a list of active tests which should be running, directing the agent to stop running tests that are not on the list and receiving from the agent a state report on running tests on the list. Additionally, instantiating and setting states of fresh primary and peer coordination FSMs using the state report from the test agent, establishing coordination interactions with additional controllers of additional test agents that are participating with the connection-interrupted agent in the active tests, and the connection-interrupted agent continuing to conduct active tests and directing results to the second controller without need to tear down and restart the active tests.Type: GrantFiled: April 8, 2021Date of Patent: May 16, 2023Assignee: Spirent Communications, Inc.Inventor: David Joyner
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Patent number: 11645177Abstract: A diagnosis circuit makes a diagnosis of a first multiplexer. The first multiplexer receives input data elements, selects one of the input data elements, and outputs the selected one as a selected data element. The diagnosis circuit includes a comparator unit and a second multiplexer. The comparator unit compares each of the input data elements to be supplied to the first multiplexer with the selected data element provided by the first multiplexer. The second multiplexer receives comparative data elements corresponding one to one to results of comparison made by the comparator unit with respect to the input data elements and outputs, out of the comparative data elements, a comparative data element, including a result of comparison between the one input data element selected by the first multiplexer and the selected data element, as a result data element.Type: GrantFiled: January 26, 2022Date of Patent: May 9, 2023Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventor: Masaaki Nagai
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Patent number: 11645156Abstract: Approaches for updating an error policy based on boot-time error information and run-time error information, are described. The error policy maps an error type with a prescribed action. In an example, the error policy is updateable based run-time error information corresponding to a computing device. The updated error policy may then be used for addressing boot-time errors of computing devices.Type: GrantFiled: January 28, 2022Date of Patent: May 9, 2023Assignee: Hewlett Packard Enterprise Development LPInventor: Debdipta Ghosh
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Patent number: 11635966Abstract: Aspects of the present disclosure provide a processor having: an execution unit configured to execute machine code instructions, at least one of the machine code instructions requiring multiple cycles for its execution; instruction memory holding instructions for execution, wherein the execution unit is configured to access the memory to fetch instructions for execution; an instruction injection mechanism configured to inject an instruction into the execution pipeline during execution of the at least one machine code instruction fetched from the memory; the execution unit configured to pause execution of the at least one machine code instruction, to execute the injected instruction to termination, to detect termination of the injected instruction and to automatically recommence execution of the at least one machine code instruction on detection of termination of the injected instruction.Type: GrantFiled: June 1, 2021Date of Patent: April 25, 2023Assignee: GRAPHCORE LIMITEDInventors: James Pallister, Jamie Hanlon
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Patent number: 11625308Abstract: An apparatus comprises a host device that includes a multi-path input-output (MPIO) driver configured to control delivery of input-output (IO) operations from the host device to first and second storage systems over selected paths through a network. The MPIO driver is further configured to identify a connectivity failure between the host device and a given one of the first and second storage systems, to generate a message comprising one or more details of the connectivity failure, and to send the message to a remaining one of the first and second storage systems over at least one path of a plurality of paths between the host device and the remaining one of the storage systems. The first and second storage systems in some embodiments are arranged in an active-active configuration relative to one another, with one being designated as a non-bias and the other as a bias storage system.Type: GrantFiled: September 14, 2021Date of Patent: April 11, 2023Assignee: Dell Products L.P.Inventor: Balasundaram Govindan
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Patent number: 11604713Abstract: A test apparatus is provided for use with a mainframe and an adapter. The test apparatus includes a logical adapter interface unit and a control system. The logical adapter interface unit is interposable between the adapter and the mainframe whereby an I/O signal transmittable from the adapter and to the mainframe is transmitted through the logical adapter interface unit. The logical adapter interface unit is configured to manipulate the I/O signal. The control system is coupled to the logical adapter interface unit and the mainframe and is configured to control manipulations of the I/O signal by the logical adapter interface unit to mimic a condition of I/O traffic being run through the adapter and to log a response of the mainframe to the manipulations.Type: GrantFiled: February 12, 2020Date of Patent: March 14, 2023Assignee: International Business Machines CorporationInventors: Andrew C. M. Hicks, Michael Peter Lyons, Miles C. Pedrone, Tynan J. Garrett
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Patent number: 11599437Abstract: A mechanism is provided for automatically detecting, diagnosing, transporting, and repairing devices having failed during burn-in testing. Embodiments provide a system that monitors devices undergoing burn-in testing and detecting when a device or a component within a device fails the burn-in test. Embodiments can then alert burn-in-rack monitor personnel of the device failure. Embodiments can concurrently determine the nature of the failure applying a machine learning-based prediction model against log files associated with the failed device. The diagnosis along with a recommended repair strategy can be provided to the repair center as an aid in accelerating the repair process. In addition, the diagnosis can be used to order parts for the repair from a parts depot. In this manner, embodiments can reduce the time for detection, diagnosis, and repair of the failed device.Type: GrantFiled: February 22, 2021Date of Patent: March 7, 2023Assignee: Dell Products L.P.Inventors: Yun Xi, Yu Huang Lin, Meng Meng Jiang, Wen Sen Que, Hua Shan Liang, Mu Shou Lan, Zhi Jian Weng, Lang Lin
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Patent number: 11593229Abstract: Data protection methods and systems for a storage environment are provided. A first-in-first out (FIFO) structure stores a logical representation of a first storage location that retains previous data for a data container, after new data for the data container is stored at a second storage location. The FIFO structure also stores a logical representation of a file system tree structure that is stored in persistent storage, after a consistent point operation. In response to an event, the file system tree structure is selected, based on the file system tree structure being closest to a transaction. A snapshot is generated using the file system tree structure. Thereafter, the data container is restored from the snapshot or from a copy of the snapshot.Type: GrantFiled: September 23, 2020Date of Patent: February 28, 2023Assignee: NETAPP, INC.Inventors: Vikhyath Rao, Nikul Y. Patel, Ananthan Subramanian, Vijayabhaskar Rao Sirigineni, Vetrivelan Kaliyaperumal
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Patent number: 11593236Abstract: Systems and processes are disclosed to preserve data integrity during a storage controller failure. In some examples, a storage controller of an active-active controller configuration can back-up data and corresponding cache elements to allow a surviving controller to construct a correct state of a failed controller's write cache. To accomplish this, the systems and processes can implement a relative time stamp for the cache elements that allow the backed-up data to be merged on a block-by-block basis.Type: GrantFiled: May 4, 2022Date of Patent: February 28, 2023Assignee: Seagate Technology LLCInventors: Adithya Uligere Narasimhamurthy, Ritvik Viswanatha, Michael Barrell
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Patent number: 11573871Abstract: A debugging method for a Universal Serial Bus (USB) device includes: receiving input information of a terminal through a Human Interface Device (HID) device; when report ID of the input information is a serial port ID, transmitting the input information to a buffer of a virtual serial port Teletype (TTY) device; and extracting the input information of the terminal from the buffer of the virtual serial port TTY device, executing a shell command on the input information, and returning execution result to the terminal through an original path. The method uses a USB interface to implement a HID device, thereby realizing drive-free execution. In addition, use of the endpoint of the HID device can save endpoints needed for additional debugging and driving.Type: GrantFiled: March 31, 2020Date of Patent: February 7, 2023Assignee: YEALINK (XIAMEN) NETWORK TECHNOLOGY CO., LTD.Inventors: Hu Jiang, Yun Liao, Huirong Zhang, Zhizhong Ouyang
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Patent number: 11573846Abstract: Techniques for predicting failure mode specific reliability characteristics of tangible equipment using parametric probability models are disclosed. In some example embodiments, a computer system receives a model training configuration entered via a user interface, trains a failure curve model for a selected failure mode of a selected equipment model based on the model training configuration at a time indicated by training schedule data, and generates analytical data for the selected failure mode of the selected equipment model using the trained failure curve model. The failure mode corresponds to a specific way in which the equipment model is capable of failing. In some example embodiments, the training of the failure curve model comprises determining a shape parameter and a scale parameter for the failure curve model based on a fitting of failure event data to a continuous probability distribution, and storing the parameters for use in generating the analytical data.Type: GrantFiled: June 20, 2022Date of Patent: February 7, 2023Assignee: SAP SEInventor: Rashmi B. Shetty
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Patent number: 11573872Abstract: In various examples, one or more components or regions of a processing unit—such as a processing core, and/or component thereof—may be tested for faults during deployment in the field. To perform testing while in deployment, the state of a component subject to test may be retrieved and/or stored during the test to maintain state integrity, the component may be clamped to communicatively isolate the component from other components of the processing unit, a test vector may be applied to the component, and the output of the component may be compared against an expected output to determine if any faults are present. The state of the component may be restored after testing, and the clamp removed, thereby returning the component to its operating state without a perceivable detriment to operation of the processing unit in deployment.Type: GrantFiled: December 20, 2021Date of Patent: February 7, 2023Assignee: NVIDIA CorporationInventors: Jonah Alben, Sachin Idgunji, Jue Wu, Shantanu Sarangi
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Patent number: 11544165Abstract: To locate an intermittent fault in a communication structure of an aircraft comprising pieces of equipment that are interconnected by cabling forming a plurality of communication media that are shared, an analyzer retrieves an error report relating to transmission errors observed on each of said communication media, performs a count of the transmission errors, per type of error and per communication chain, computes a median of the counts for communication chains comprising the same pair of wired pieces of equipment, and when, for a communication chain, the count exceeds a threshold equal to the median plus a predefined margin, generates an alarm indicating detection of an intermittent fault in association with the communication chain that led the threshold to be exceeded. Thus, intermittent faults are easily located and repaired.Type: GrantFiled: June 24, 2020Date of Patent: January 3, 2023Assignee: AIRBUS OPERATIONS SASInventors: Philippe Passemard, Alvaro Ruiz Gallardo
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Patent number: 11537478Abstract: In the face of ransomware attacks, which can be increasingly difficult to effectively prevent, a solution can be considered to be the minimization of the cost and time taken to recover data and, hence business activities. Embodiments perform a restore operation that include automatically identifying the most recent healthy backup, from which data should be restored, and the prioritizing of the order in which data should be restored.Type: GrantFiled: August 21, 2020Date of Patent: December 27, 2022Assignee: EMC IP HOLDING COMPANY LLCInventors: Niamh O'Mahony, Andrew Byrne, Regis Wenner, Celine Brandy
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Patent number: 11513927Abstract: Techniques described herein relate to a method for performing testing operations for information handling systems.Type: GrantFiled: January 25, 2022Date of Patent: November 29, 2022Assignee: Dell Products L.P.Inventors: Ramakanth Kanagovi, Guhesh Swaminathan, Saheli Saha, Jason Fay, Araiz Baqi, Sankunny Jayaprasad
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Patent number: 11500747Abstract: A computing system initialization system includes a computing device that is coupled to a management device and that includes a processing system having at least one register storing debug-message-display-determination instructions, and a memory system that is coupled to the processing system and that includes Basic Input/Output System (BIOS) instructions that, when executed by the processing system, cause the processing system to provide a BIOS engine. The BIOS engine begins initialization operations and, during those initialization operations, generates at least one first debug message. The BIOS engine then accesses the at least one register included in the processing system to execute the debug-message-display-determination instructions and, in response, determines that the at least one first debug message should be displayed. In response, the BIOS engine transmits the at least one first debug message to the management device such that the management device displays the at least one first debug message.Type: GrantFiled: January 30, 2020Date of Patent: November 15, 2022Assignee: Dell Products L.P.Inventors: Jing-Hui Lee, Shih-Chieh Hsu
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Patent number: 11487621Abstract: An information handling system may include at least one processor, a memory, and an embedded controller (EC). The information handling system may be configured to, prior to initialization of an operating system of the information handling system: execute memory reference code configured to test selected regions of the memory; transmit results of the memory reference code to the EC; store, at the EC, information indicative of respective likelihoods that particular regions of the memory are bad; and upon a subsequent boot, select a region of the memory having a low likelihood of being bad for loading a Basic Input/Output System (BIOS) of the information handling system.Type: GrantFiled: April 29, 2021Date of Patent: November 1, 2022Assignee: Dell Products L.P.Inventors: Adolfo Montero, Michael Arms, Balasingh P. Samuel
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Patent number: 11474875Abstract: A system for dynamically load-balancing at least one redistribution element across a group of computing resources that facilitates at least an aspect of an Industrial Execution Process in an M:N working configuration is illustrated.Type: GrantFiled: August 11, 2021Date of Patent: October 18, 2022Assignee: Schneider Electric Systems USA, Inc.Inventors: Raja Ramana Macha, Andrew Lee David Kling, Frans Middeldorp, Nestor Jesus Camino, Jr., James Gerard Luth, James P. McIntyre
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Patent number: 11474915Abstract: Example implementations relate to management of clusters. A cluster recovery manager may comprise a processing resource; and a memory resource storing machine-readable instructions to cause the processing resource to: adjust, based on a monitored degree of performance of a controller of a controller cluster, a state of the controller to one of a first state and a second state; and reassign a corresponding portion of a plurality of APs managed by the controller periodically to a different controller until the state of the controller is determined to be adjustable to the first state. The reassignment can be triggered responsive to a state adjustment of the controller from the first state to the second state.Type: GrantFiled: August 28, 2018Date of Patent: October 18, 2022Assignee: Hewlett Packard Enterprise Development LPInventors: Srinivas Rao Killadi, Sree Vasthav Shatdarshanam Venkata, Indu Shree Akasapu