Patents Examined by Indranil Chowdhury
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Patent number: 11474914Abstract: A circuit device 100 includes an interface circuit 160 that receives image data and information for image check and a processing circuit 105 that performs image check processing. The information for image check includes information for designating an image check method for a region to be subjected to image check and position information of the region to be subjected to image check. The processing circuit 105 performs the image check processing on the image data of the region to be subjected to image check specified by the position information, using the image check method designated by the designation information.Type: GrantFiled: August 9, 2019Date of Patent: October 18, 2022Assignee: SEIKO EPSON CORPORATIONInventor: Hideki Ogawa
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Patent number: 11461203Abstract: Disclosed is a systems and methods of distributed data storage using multi-layers consistent hashing comprising: a plurality of storage nodes providing data storage and redundancy protection; a plurality of management nodes maintaining the properties of the storage nodes and mapping information from virtual groups to storage nodes; a plurality of monitor nodes maintaining the state of storage nodes and handling the changes of states of storage nodes including joining, decommissioning and failure; and one or more clients providing entries for applications or users to access the storage system. The storage nodes is in a hierarchical tree arrangement, and each storage node in each layer of the tree is allocated with a plurality of identities and configured for remaining hash space with consistency. Instead of sharing one hash space among all storage nodes, there are a plurality of hash spaces kept consistent in each layer of the storage hierarchical tree.Type: GrantFiled: July 10, 2018Date of Patent: October 4, 2022Assignee: HERE DATA TECHNOLOGYInventors: Bin Hao, Jian Zhu, Jingyao Zhang
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Patent number: 11455203Abstract: A system analysis support device includes a data acquisition part that obtains time series data (items) measured in a system that is to be analyzed, an overall abnormality degree calculation part that calculates transition of abnormality degree representing overall abnormality degree of the system that is to be analyzed, using a predictive model generated so that, with 2 or more time series data (items) as input, values representing a relationship between the 2 or more time series data (items) are outputted, and the time series data (items), and a representative index selection part that selects and presents time series data (items) indicating change similar to transition of the overall abnormality degree of the system that is to be analyzed, from among the time series data (items).Type: GrantFiled: September 13, 2017Date of Patent: September 27, 2022Assignee: NEC CORPORATIONInventor: Katsuhiro Ochiai
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Patent number: 11449403Abstract: A method and system for detecting faults in a communication interface is disclosed. The communication interface is connected to a field device and a device bus comprising generating periodic diagnostic pulse by a programing unit. The programming unit is communicatively connected to the controller and a controller interface and provides the diagnostic pulse to a multiplexer to periodically apply the diagnostic pulses from the programming unit to a first winding of a transformer. The programming unit provides the diagnostic pulse to the isolation unit. A sensing unit senses a voltage drop across a sense resistor, the sensing unit having an input connected to the sense resistor and an output connected to the programming unit. The sensing unit communicates a sense signal based on the comparison to the programming unit, and switches from a primary or a secondary module to the other based on the sense signal.Type: GrantFiled: October 9, 2019Date of Patent: September 20, 2022Assignee: Honeywell International Inc.Inventors: Amit Kulkarni, Ganesh Ratilal Patil, Mohammed Rizwan, Vimal Kant
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Patent number: 11449404Abstract: A processor unit includes a memory and an ALU coupled with the memory. The processor unit also comprises a test controller, a test control register, and a signature register. The test controller manages a series of steps to test the processor unit. It overrides an ALU control signal with a replacement ALU control signal, stored in the test control register. It generates a test pattern and writes it to a memory address. It reads memory output data from the memory address, and forwards it to the ALU. The ALU executes an operation on the memory output data based on the replacement ALU control signal. The ALU output provides a test result, which is compressed to obtain a test signature, and stored in the signature register.Type: GrantFiled: October 14, 2021Date of Patent: September 20, 2022Assignee: SambaNova Systems, Inc.Inventors: Thomas Alan Ziaja, Dinesh Rajasavari Amirtharaj
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Patent number: 11429490Abstract: An information handling system may include a processor, a basic input/output system (BIOS) comprising a program of instructions executable by the processor and configured to cause the processor to initialize components of the information handling system; and a management controller communicatively coupled to the processor and configured to, during a pre-Extensible Firmware Interface Initialization (PEI) phase of the BIOS, operate as a network proxy for the BIOS to allow the BIOS to communicate data via an out-of-band network interface of the management controller.Type: GrantFiled: August 2, 2021Date of Patent: August 30, 2022Assignee: Dell Products L.P.Inventors: Ibrahim Sayyed, Sumanth Vidyadhara, Adolfo S. Montero
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Patent number: 11416433Abstract: The performance of a wireless dock can be enhanced when a USB mass storage device is connected to the wireless dock. Filter drivers can be loaded on the USB stacks of a computing device and the wireless dock to perform functionality for reducing the number of communications that are sent over a wireless network when a USB mass storage device is connected to the computing device via the wireless dock. This reduction in the number of communications can be accomplished without jeopardizing data integrity or compliance with governing protocols.Type: GrantFiled: September 2, 2020Date of Patent: August 16, 2022Assignee: Dell Products L.P.Inventors: Gokul Thiruchengode Vajravel, Vivek Viswanathan Iyer
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Patent number: 11403158Abstract: Discrete logic safety systems for smart process control devices are disclosed. A discrete logic safety system includes a heartbeat monitor to be operatively coupled to a processor of the process control device to monitor a first condition of the processor, a sensor monitor to be operatively coupled to a sensor of the process control device to monitor a second condition of the sensor, and first discrete logic operatively couple to the heartbeat monitor and the sensor monitor to generate a failure indication associated with the process control device based on the first condition or the second condition.Type: GrantFiled: July 23, 2020Date of Patent: August 2, 2022Assignee: FISHER CONTROLS INTERNATIONAL LLCInventors: Kurtis Jensen, William Sean Raymond, Eric Strong, Greg Jacobs
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Patent number: 11392472Abstract: A test controller functionally tests components of a modular data center (MDC) that is being manufactured. Functional test(s) for quality assurance of an environmental control system (ECS) are determined for an information technology pre-assembled component (ITPAC) module and an environmental system (ES) module that are configured for being coupled together for cooling of heat-generating equipment of the ITPAC module at a deployed location. For each functional test(s), the test controller identifies input signal value(s) associated with one of the modules. The test controller emulates, via a communication test cable connected between the one module and the test controller, the identified input signal value(s). The test controller determines, via the communication test cable, any response by the one module to the input signal value(s). The test controller compares the determined response to an expected response and generates and outputs test data based on the comparison.Type: GrantFiled: November 15, 2019Date of Patent: July 19, 2022Assignee: Dell Products, L.P.Inventors: Jeffery T. Sayles, Mario E. Salazar Granados
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Patent number: 11392467Abstract: Failover between decentralized identity stores in the context of there being multiple decentralized identity stores that are each under the control of a single decentralized identity to store data belonging to or regarding the decentralized identity. Third parties can use the decentralized identity to at least conditionally access the data of the primary decentralized identity store. However, in response to detecting a failover event, one of the remaining decentralized identity stores is promoted as the new primary decentralized identity store. As part of this promotion, the new primary decentralized identity store replaces the old primary decentralized identity store as being the decentralized identity store that is accessed using the decentralized identity.Type: GrantFiled: April 17, 2019Date of Patent: July 19, 2022Assignee: Microsoft Technology Licensing, LLCInventors: Brandon Murdoch, Ankur Patel, Daniel James Buchner
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Patent number: 11385950Abstract: Techniques for predicting failure mode specific reliability characteristics of tangible equipment using parametric probability models are disclosed. In some example embodiments, a computer system receives a model training configuration entered via a user interface, trains a failure curve model for a selected failure mode of a selected equipment model based on the model training configuration at a time indicated by training schedule data, generating, and generates analytical data for the selected failure mode of the selected equipment model using the trained failure curve model. The failure mode corresponds to a specific way in which the equipment model is capable of failing. In some example embodiments, the training of the failure curve model comprises determining a shape parameter and a scale parameter for the failure curve model based on a fitting of failure event data to a continuous probability distribution, and storing the parameters for use in generating the analytical data.Type: GrantFiled: April 20, 2021Date of Patent: July 12, 2022Assignee: SAP SEInventor: Rashmi B. Shetty
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Patent number: 11379295Abstract: Generally described, the present disclosure relates to the use of a virtual machine monitor to instruct one or more virtual processing units belonging to a malfunctioning virtual machine instance to pause processing. While paused, the virtual machine monitor may store the register data of the virtual processing units to virtual memory of the virtual machine instance (e.g., perform a register dump on behalf of the virtual processing units of the malfunctioning virtual machine instance). The virtual machine monitor may then instruct virtual processing units to reinitialize and invoke protected software (e.g., a crash kernel) from virtual memory in an effort to recover from virtual memory the register data dumped there by the VM monitor.Type: GrantFiled: May 15, 2019Date of Patent: July 5, 2022Assignee: Amazon Technologies, Inc.Inventor: David William Martin Woodhouse
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Patent number: 11341013Abstract: A debugging device includes a plurality of debug units, a UART port, and a processor. The debugging device is communicated with an electronic device through the UART port. The processor can receive debug signals from the terminal through the UART port, generate a plurality of debug controlling commands based on the debug signals, and send the plurality of debug controlling commands to the plurality of debug units, for controlling the plurality of debug units to debug the electronic device according to the plurality of debug controlling commands.Type: GrantFiled: October 28, 2019Date of Patent: May 24, 2022Assignee: Fulian Precision Electronics (Tianjin) Co., LTD.Inventor: Xiao-Long Zhou
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Patent number: 11334455Abstract: Described herein is a computer implemented method for repairing data inconsistency between a first mirror node and a primary cluster. The method comprises retrieving a snapshot of the one or more objects from a primary cluster; determining from the snapshot of the objects, one or more operations for the mirror node to perform to ensure data consistency between the mirror node and the primary cluster; and performing the operations.Type: GrantFiled: September 18, 2020Date of Patent: May 17, 2022Assignees: ATLASSIAN PTY LTD., ATLASSIAN INC.Inventors: Richard Friend, Bryan Turner, Manish Goyal
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Patent number: 11334444Abstract: Embodiments of the present disclosure relate to a method, device and computer program product for managing storage systems. A method comprises, in response to receiving a command to recover a storage system, reading first configuration information from a first disk of the storage system to be recovered, the first configuration information indicating a first disk array group to which the first disk belongs. The method further comprises recovering the first disk array group based at least on the first configuration information. The method further comprises, in response to the first disk array group being recovered, reading second configuration information from the first disk array group, the second configuration information indicating a storage resource pool to which the first disk array group belongs. Additionally, the method further comprises recovering the storage resource pool based at least on the second configuration information.Type: GrantFiled: October 30, 2018Date of Patent: May 17, 2022Assignee: Dell Products L.P.Inventors: Bernie Hu, Vicent Wu, Olivia Juan Huang, Amber Jing Li, Ying Yu
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Patent number: 11334452Abstract: A tool for performing remote part reseat actions. Responsive to receiving a request for a scheduled operation, the tool generates an operation table in a push file. Responsive to a determination that there is at least one redundant component for the scheduled operation, the tool identifies the at least one redundant component. The tool determines one or more tolerable errors for the at least one redundant component. The tool appends the at least one redundant component and the one or more tolerable errors to the operation table in the push file. The tool schedules the push file to prescribe one or more recovery operations for the scheduled operation.Type: GrantFiled: June 8, 2021Date of Patent: May 17, 2022Assignee: International Business Machines CorporationInventors: Kelly Vaughn, Michael Kane, Dane Warren, Thomas Mathias
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Patent number: 11327862Abstract: Disclosed herein are vector index registers for storing or loading indexes of true and/or false results of conditional operations using multiple lane processing in vector processors. Each of the vector index registers store multiple addresses for accessing multiple positions in operand vectors in various types of operations that can leverage multi-lane processing.Type: GrantFiled: May 20, 2019Date of Patent: May 10, 2022Assignee: Micron Technology, Inc.Inventor: Steven Jeffrey Wallach
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Patent number: 11327858Abstract: Systems and processes are disclosed to preserve data integrity during a storage controller failure. In some examples, a storage controller of an active-active controller configuration can back-up data and corresponding cache elements to allow a surviving controller to construct a correct state of a failed controller's write cache. To accomplish this, the systems and processes can implement a relative time stamp for the cache elements that allow the backed-up data to be merged on a block-by-block basis.Type: GrantFiled: August 11, 2020Date of Patent: May 10, 2022Assignee: Seagate Technology LLCInventors: Adithya Uligere Narasimhamurthy, Ritvik Viswanatha, Michael Barrell
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Patent number: 11321178Abstract: Occurrence of a RAID double failure in a slice of a RAID protection group (failed slice) renders data stored in the back-end tracks of the failed slice vulnerable to loss. When a RAID double failure is detected, a new slice is added to the RAID protection group. Front-end tracks that map to the good back-end tracks of the failed slice are moved from the back-end tracks of the failed slice to the back-end tracks of the newly added slice. Any front-end tracks that mapped to the bad back-end tracks of the failed slice are made to be write pending and written to corresponding back-end tracks of the newly added slice. Front-end tracks that map to the bad back-end tracks may be made to be write-pending in connection with a host write operation, by reading the front-end tracks from a local backup, or from a remote backup location.Type: GrantFiled: June 29, 2021Date of Patent: May 3, 2022Assignee: Dell Products, L. P.Inventors: Rong Yu, Peng Wu, Shao Hu, Lixin Pang
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Patent number: 11321179Abstract: A circuit at an interface between a device and an interconnect fabric is configured to track outstanding transactions associated with the device and ensure the completion of the outstanding transactions before rebooting or powering down the device. In some embodiments, the circuit is also configurable to provide appropriate responses when the device is powered down or is being rebooted such that other devices in the system can still operate even without knowing that the device is inactive and would not hang because no response is received from the device.Type: GrantFiled: August 24, 2020Date of Patent: May 3, 2022Assignee: Amazon Technologies, Inc.Inventors: Kun Xu, Thomas A. Volpe, Ron Diamant, Mark Anthony Banse