Abstract: A circuit arrangement and method bypass the storage of requested data in a higher level cache of a multi-level memory architecture during the return of the requested data to a requester, while caching the requested data in a lower level cache. For certain types of data, e.g., data that is only used once and/or that is rarely modified or written back to memory, bypassing storage in a higher level cache reduces the likelihood of the requested data casting out frequently used data from the higher level cache. By caching the data in a lower level cache, however, the lower level cache can still snoop data requests and return requested data in the event the data is already cached in the lower level cache.

Abstract: A storage system including: a disk device including an original volume and a plurality of snapshot generations; and a storage control unit which includes a processor unit. The processor unit receives write data to a storage area of the original volume, and determines whether data stored in the storage area of the original volume is already copied to the snapshot volume or not; if the data stored in the storage area of original volume is not already copied to snapshot volume, the processor unit copies the data from original volume to the snapshot volume, when a use capacity of the snapshot volume is larger than threshold amount by the copy, the processor unit indicates a specified snapshot generation, the processor unit migrates data of the specified snapshot generation from the snapshot volume to tape device; the processor unit deletes information of the specified snapshot generation in the snapshot volume.

Abstract: Embodiments of the present invention set forth systems and methods for compressing thread group data written to frame buffer memory to increase overall memory performance. A compression/decompression engine within the frame buffer memory interface includes logic configured to identify situations where the threads of a thread group are writing similar scalar values to memory. Upon recognizing such a situation, the engine is configured to compress the scalar data into a form that allows all of the scalar data to be written to or read from the frame buffer memory in fewer clock cycles than would be required to transmit the data in uncompressed form to or from memory. Consequently, the disclosed systems and methods are able to effectively increase memory performance when executing thread group STORE and LOAD operations.

Abstract: A data storage device has a host controller interface, a plurality of microprocessor units each having a portion of random access memory (RAM) dedicated thereto, a plurality of Flash device configurations each having dedicated bus connections to individual ones or multiples of the microprocessor units, and a dataflow controller accessible to the host controller interface for managing access to the Flash device configurations.

Abstract: A single micro-instruction to perform either an N-bit or a 2N-bit load is provided. A microprocessor having an N-bit load port performs either an N-bit load or a 2N-bit load in a single cycle with the same micro-instruction being used for both the N-bit and the 2N-bit load.

Abstract: In one embodiment, a system comprises one or more input/output (I/O) devices; an I/O memory management unit (IOMMU) coupled to receive memory requests sourced by the I/O devices and configured to provide address translation for the memory requests; and a virtual machine monitor (VMM) configured to manage one or more virtual machines on the system, wherein the VMM is configured to virtualize the IOMMU, providing one or more virtual IOMMUs for use by one or more virtual machines.

Abstract: Embodiments of the invention generally provide a system, method and memory device for accessing memory. One embodiment includes synchronization circuitry configured to determine timing skew between a first memory device and a second memory device, and introduce a delta delay to at least one of the first memory device and the second memory device to adjust the timing skew.

Abstract: A cache module for a central processing unit has a cache control unit coupled with a memory, and a cache memory coupled with the control unit and the memory, wherein the cache memory has a plurality of cache lines, at least one cache line of the plurality of cache lines has an address tag bit field and an associated storage area for storing instructions to be issued sequentially and at least one control bit field, wherein the control bit field is coupled with the address tag bit field to mask a predefined number of bits in the address tag bit field.

Abstract: A network device includes an alignment module to align payloads of received frames on memory boundaries in a buffer memory. The frames may be Ethernet frames which encapsulate IP (Internet Protocol) packets as payloads. The alignment module modifies the frame to shift the IP payload into a position in the memory regions such that the IP payload is aligned with the memory boundaries. The number x of non-data bits can be determined according to x=m*c+p, where m is the bit depth of memory regions, n is the length of a header, p is the non-zero remainder of the ratio n/m, and c is an integer.

Abstract: A storage controller that can control memory addresses even when a memory module having a different device configuration than an already mounted memory module is added as an expansion module. More specifically, a storage controller for controlling a storage unit that can be constructed using a plurality of memory modules is configured so as to include: a register which stores memory module configuration information for a basic memory module and an expansion memory module independently of each other; and an address conversion unit which, based on the memory module configuration information stored in the register, generates an address that can access the storage unit even when the memory address space of the expansion memory module is different from the memory address space of the basic memory module.

Abstract: A method for providing field updates through the use of a memory emulation circuit with a content addressable memory (CAM) as the intelligent portion of the emulation circuit's arbiter. CAM circuit 200 is comprised of configurable memory and is initially unprogrammed. Address requests are passed straight through multiplexer 201 to Read Only Memory (ROM) 202. As a result the data in the data location in ROM 202 that corresponds to the requested address will be output to data bus 205. If data locations in ROM 202 become defective or contain data that needs to be upgraded the circuit implements a remapping of the data location. CAM circuit 200 is programmed with direct addresses to be replaced in ROM 202. The direct addresses are paired to emulation addresses of data locations in configurable memory 203. Upgraded or substitute data is programmed into the configurable memory 203 at the paired emulation address.

Abstract: A dynamic cache system is configured to flexibly respond to changes in operating parameters of a data storage and retrieval system. A cache controller in the system implements a caching policy describing how and what data should be cached. The policy can provide different caching behavior based on exemplary parameters such as a user ID, a specified application or a given workload. The cache controller is coupled to the data path for a data storage system and can be implemented as a filter in a filter framework. The cache memory for storing cached data can be local or remote from the cache controller. The policies implemented in the cache controller permit an application to control caching of data to permit optimization of data flow for the particular application.

Abstract: A first storage system misrepresents an identifier of the storage system and an identifier of a volume and provides the host computer with a first volume. A second storage system misrepresents an identifier of the storage system and an identifier of a second volume as being identical to those misrepresented by the first storage system and provides the host computer with a second volume. A management computer acquires, upon detection of a failure in an access, a status of copying, a status of the first storage system, and a status of the second storage system and controls an access from the host computer with reference to the plurality of acquired statuses. Accordingly, even when a fault occurs in one of the two storage systems, a network that connects the two storage systems, or the like, the host computer can access to latest data.

Abstract: A data processing system with memory access comprising an operating system for supporting processes, such that the process are associated with one or more resources and the operating system being arranged to police the accessing by processes of resources so as to inhibit a process from accessing resources with which it is not associated. Part of this system is an interface for interfacing between each process and the operating system and a memory for storing state information for at least one process. The interface may be arranged to analyze instructions from the processes to the operating system, and upon detecting an instruction to re-initialize a process cause state information corresponding to that pre-existing state information to be stored in the memory as state information for the re-initialized process and to be associated with the resource.

Abstract: A storage apparatus includes a storage unit and a controller, wherein control of inputting/outputting data from/to a device provided in said storage unit is executed in accordance with a request received by said storage apparatus. An actual device of the storage apparatus corresponds to a virtual device which is external to said storage apparatus. The controller operates to perform a process for mapping an actual device address corresponding to a virtual device address, in accordance with a specification of the actual device to be mounted or unmounted to correspond to the virtual device, and storing and retaining mapping information obtained from the mapping in a first table. The controller also performs data input/output process for receiving, an access request for data input/output in which said virtual device address is specified, obtaining the actual device address mapped to said specified virtual device address in said first table, and accessing the actual device by said obtained actual device address.

Abstract: A system for implementing a memory subsystem command interface, the system including a cascaded interconnect system including one or more memory modules, a memory controller and a memory bus. The memory controller generates a data frame that includes a plurality of commands. The memory controller and the memory module are interconnected by a packetized multi-transfer interface via the memory bus and the frame is transmitted to the memory modules via the memory bus.

Abstract: A multipath accessible semiconductor memory device having a mailbox area and a mailbox access control method thereof are provided. The semiconductor memory device includes N number of ports, at least one shared memory area allocated in a memory cell array, and N number of mailbox areas for message communication. The at least one shared memory area is operationally connected to the N number of ports, and is accessible through a plurality of data input/output lines to form a data access path between the at least one shared memory area and one port, having an access right to the at least one memory area, among the N number of ports. The N number of mailbox areas are provided in one-to-one correspondence with the N number of ports and are accessible through the plurality of data input/output lines when an address of a predetermined area of the at least one shared memory area is applied to the semiconductor memory device. An efficient layout of mailboxes and an efficient message access path can be obtained.

Abstract: In a method of synchronizing with a separated disk cache, the separated cache is configured to transfer cache data to a staging area of a storage device. An atomic commit operation is utilized to instruct the storage device to atomically commit the cache data to a mapping scheme of the storage device.

Abstract: An improved RAID storage system adapted to selectively and automatically store the same data “in tandem” using two different storage profiles. In one embodiment, a first store operation occurs in accordance with first storage profile and, if a flag in the first storage profile is set, a second store operation automatically occurs in accordance with a second storage profile but with the same data as stored in the first store operation. The first and second storage profiles are stored sequentially in profile registers within a controller in the storage system. To speed the tandem operation, the data may be held in a re-readable FIFO buffer in the controller. The buffer is sized to hold the minimum size of data that can be stored to the physical disks in the storage system. Preferably, the size of the buffer is substantially equal to the minimum size.

Abstract: A method and system of managing data access in a shared memory cache of a processor are disclosed. The method includes probing one or more memory addresses that map to a subset of the shared memory cache and sensing a plurality of events in the one or more memory addresses. Cache utilization information is then obtained by reading a hardware performance counter of the processor. The hardware performance counter is incremented based on the occurrence of the plurality of events. Based upon the cache utilization information, an occurrence of one of the plurality of events is reduced.