Abstract: A system and method for cache replacement includes: augmenting each cache block in a cache region with a region hint indicating a temporal priority of the cache block; receiving an indication that a cache miss has occurred; and selecting for eviction the cache block comprising the region hint indicating a low temporal priority.

Abstract: Described are techniques for managing data in a data storage system. While the data storage system is operating in a first mode, portions of cached write data not yet destaged to a data storage device are copied from the volatile memory cache to a first area in a flash-based memory. In response to a vault operation event, the data storage system operates in a second mode in which all remaining portions of cached write data from the volatile memory cache not currently included in the first area are copied to a second area of the flash-based memory.

Abstract: A method, system, and machine-readable medium for controlling access to data of a tape data storage medium are disclosed. In accordance with one embodiment, a method is provided which comprises conveying data access control metadata from a tape cartridge comprising a tape data storage medium to a host, receiving decrypted metadata from the host, comparing a checksum value determined utilizing the decrypted metadata with checksum data stored within the tape cartridge; and processing a request to access the tape data storage medium received from the host based upon a comparison of the checksum value and checksum data. In the described method embodiment, the data access control metadata comprises encrypted metadata corresponding to a data storage parameter, where data is stored within the tape data storage medium utilizing the data storage parameter and the decrypted metadata is generated by the host utilizing the encrypted metadata.

Abstract: A storage device has a storage medium, a plurality of read-write mechanisms, a quality monitoring and book-keeping unit and a scheduling unit. The plurality of read-write mechanisms is coupled to the storage medium. The quality monitoring and book-keeping unit is coupled to the plurality of read-write mechanisms and is adapted to monitor at least one performance parameter associated with each read-write mechanism during operation. The scheduling unit is coupled to the quality monitoring and book-keeping unit. The scheduling unit is adapted to rank each of the plurality of read-write mechanisms according to the at least one performance parameter and to responsively schedule use of a read-write mechanism according to its rank.

Abstract: In one embodiment, the present invention includes a method for receiving a snoop request, providing the snoop request to a coherency engine along a first path and providing the snoop request to a bypass logic along a bypass path, and generating a speculative invalid snoop response in the bypass logic and forwarding the speculative invalid snoop response to indicate that an address associated with the snoop response is not present in a cache memory. Other embodiments are described and claimed.

Abstract: In one embodiment, the present invention includes a method for receiving a request for data in a home agent of a system from a first agent, prefetching the data from a memory and accessing a directory entry to determine whether a copy of the data is cached in any system agent, and forwarding the data to the first agent without waiting for snoop responses from other system agents if the directory entry indicates that the data is not cached. Other embodiments are described and claimed.

Abstract: Apparatus, systems, and methods may operate to assign a plurality of managing nodes to manage a corresponding plurality of groups of blocks forming a portion of a snapshot volume for copy-on-write execution and snapshot write execution. Further operations include coordinating the copy-on-write execution and the snapshot write execution using a write completion map accessible to the managing nodes. Additional apparatus, systems, and methods are disclosed.

Abstract: A method of recording, and an apparatus to record, data on a write-once disc, and the write-once disc used with the method and apparatus. The write-once disc includes a plurality of update areas in which to record a predetermined type of updated information, at least one main access information area (AIA) in which to record main access information (AI), the main AI indicating a final update area in which finally updated information is recorded, among the plurality of update areas, and at least one sub AIA in which to record sub AI, the sub AI indicating a location of the finally updated information recorded in the final update area.

Abstract: Technologies are presented herein for synchronization of I/O operations in a data storage system. Multiple reader and writer locks may be acquired by calling processes at two different granularities. Locks may be acquired for an area of storage equivalent to the logical unit of allocation or for a sub-provision area equivalent to a unit of snapshot read-modify-write. Each lock may be represented by a lock data structure that represents the same amount of logical address space as the logical unit of allocation. A request that arrives to the lock data structure may be placed in a lock wait queue until the request can be honored. A round robin technique may be utilized to respond to requests for locks so that one lock does not starve out other locks.

Abstract: A data processing apparatus is provided wherein processing circuitry executes multiple program threads including at least one high priority thread and at least one lower priority thread. Instructions required by the threads are retrieved from a cache memory hierarchy comprising multiple cache levels. The cache memory hierarchy includes a bypass path for omitting a predetermined level of the cache memory hierarchy when performing a lookup procedure for a required instruction and for bypassing said predetermined level of the cache memory hierarchy when returning said required instruction to said processing circuitry. The bypass path is used by default when the requested instruction is for a lower priority thread.

Abstract: Methods, systems, and computer program products to provide temporal storage in a fabric-based virtualization environment are presented. Such capacity is provided through the association of a temporal storage appliance, which is configured as a member of a linked VLUN with a non-temporal disk volume. The linked VLUN is provided by a virtualizing fabric switch to a network node such as a network node.

Abstract: An apparatus and a method for managing a storage space through time-variant consumption estimation. More particularly, an apparatus and a method for managing a storage space through time-variant consumption estimation that estimates consumption of an entire storage space when a user instructs program editing, program recording or reserved recording, and so on. When there is a possibility that the estimated consumption exceeds a predetermined value, immediately providing a user with information indicating that the storage space is lacking. The apparatus includes a storage unit storing contents in the storage space, a consumption estimation unit estimating time-variant consumption of the storage space, a contents management unit deleting at least a portion of the contents or storing at least a portion of additionally input contents according to the estimation result, and an output unit outputting the deletion or storage result.

Abstract: In a computer including a processor for executing a program and a storage that includes a first storage area and a second storage area for storing objects generated by the executed program, the processor stores objects generated by executing the program in the first storage area. If an object stored in the first storage area is accessed, the processor records access information of the accessed object. The processor extracts a leak object having a high possibility of memory leak on the basis of the recorded access information, and moves the extracted leak object to the second storage area.

Abstract: A DRAM controller may be configured to re-order read/write requests to maximize the number of page hits and minimize the number of page conflicts and page misses. A three-level prediction algorithm may be performed to obtain auto-precharge prediction for each read/write request, without having to track every individual page. Instead, the DRAM controller may track the history of page activity for each bank of DRAM, and make a prediction to first order based history that is not bank based. The memory requests may be stored in a queue, a specified number at a time, and used to determine whether a page should be closed or left open following access to that page. If no future requests in the queue are to the given bank containing the page, recent bank history for that bank may be used to obtain a prediction whether the page should be closed or left open.

Abstract: A caching method provides a cashing mechanism between a logical addresses and a flash memory physical addresses. The caching mechanism involves a search tree which contains a number of internal and external translation nodes. Each external translation node points to a link list of translation units, and each translation unit records a range of logical addresses and the corresponding range of physical addresses, in addition to a version value. By traversing the search tree to reach a translation unit, the physical address of a target logical address can be determined in an efficient manner. The version value of the translation unit can be used to determine the space taken up for storing the mapping of the logical and physical addresses should be released for reuse.

Abstract: A data processing system includes a multiport memory module including a plurality of first ports and a plurality of second ports. The data processing system includes a plurality of first buses and a plurality of second buses. A plurality of hardware acceleration modules configured to communicate with respective ones of the plurality of first ports via respective ones of the plurality of first buses. The data processing system includes a processor module. A random access memory (RAM) module configured to store data. The processor module and the RAM module communicate with the multiport memory module via respective ones of the plurality of second buses. A shared bus includes a first bus portion configured to communicate with the plurality of hardware acceleration modules at a first rate. A second bus portion configured to communicate with the processor module and the RAM module at a second rate that is different than the first rate.

Abstract: The present invention relates to a mapping information managing apparatus and method for a non-volatile memory supporting different cell types, and more particularly, to a mapping information managing apparatus and method for a non-volatile memory supporting different cell types capable of managing mapping information considering physical characteristics of each cell type in the non-volatile memory supporting different cell types in which bits represented by one cell are different from each other. A mapping information managing apparatus for a non-volatile memory supporting different cell types includes: a user request unit used for a user to request a predetermined operation by using a logical address; a non-volatile memory comprising a plurality of memory areas having different cell types; and a mapping information managing unit storing mapping information on user data written to a second memory area of the plurality of memory areas in a first memory area.

Abstract: A computer implemented method, data processing system, and computer usable program code are provided for storing data items in a computer. A plurality of hash functions of data values in a data item are computed. A corresponding memory location is determined for one of the plurality of hash functions. The data item and a key portion and a payload portion of all data items are stored contiguously within the memory location. Also provided for are retrieving data items in a computer. A plurality of hash functions of data values in a probe key are computed. A corresponding memory location is determined for each of the plurality of hash functions. Data items in each memory location are examined to determine a match with the probe key. Responsive to a match, a payload of the matching stored data item is returned. All of the steps are performed free of conditional branch instructions.

Abstract: A data recording apparatus includes a determining unit that determines whether a storable area is present in the first storage device. The storable area is a combination of a plurality of empty areas having contiguous physical addresses with a total data volume larger than that of a volume of the data. When the determining unit determines that the storable area is present, a first storage unit stores the data in the storable area, and a second storage unit stores the data that has been stored by the first storage unit in the storable area as a lump into the second storage device.

Abstract: A computer implemented method, data processing system, and computer usable program code are provided for storing data items in a computer. A plurality of hash functions of data values in a data item are computed. A corresponding memory location is determined for one of the plurality of hash functions. The data item and a key portion and a payload portion of all data items are stored contiguously within the memory location. Also provided for are retrieving data items in a computer. A plurality of hash functions of data values in a probe key are computed. A corresponding memory location is determined for each of the plurality of hash functions. Data items in each memory location are examined to determine a match with the probe key. Responsive to a match, a payload of the matching stored data item is returned. All of the steps are performed free of conditional branch instructions.