Abstract: A display substrate and a display device. The display substrate includes a display region, a first connecting wire, and a second connecting wire. A first display region includes a first sub-pixel array, including a plurality of light emitting elements arranged in an array, and the plurality of light emitting elements include a first light emitting element and a second light emitting element. The second display region includes a first pixel circuit array, including a plurality of first pixel circuit units, and the plurality of pixel circuit units include a first pixel circuit (D10) and a second pixel circuit. The first connecting wire (151) is connected to the first pixel circuit and the first light emitting element. The second connecting wire is connected to the second pixel circuit and the second light emitting element. The second connecting wire extends in a first direction, the first connecting wire extends in a second direction.

Abstract: A display apparatus includes a substrate including a display area and a sensor area, the display area including main pixels and the sensor area including auxiliary pixels and a transmission portion; a first pixel electrode and a first emission layer in each of the main pixels; a second pixel electrode and a second emission layer in each of the auxiliary pixels; an opposite electrode integrally arranged in the display area and the sensor area; and a metal layer at least partially surrounding the transmission portion, wherein the opposite electrode has an opening corresponding to the transmission portion.

Abstract: A semiconductor device includes a semiconductor region made of a material to which conductive impurities are added, an insulating film formed on a surface of the semiconductor region, and an electroconductive gate electrode formed on the insulating film. The gate electrode is made of a material whose Fermi level is closer to a Fermi level of the semiconductor region than a Fermi level of Si in at least a portion contiguous to the insulating film.

Abstract: The present invention relates to a method for connecting an electrical contact to a nanomaterial carried by a substrate. At least one layer of soluble lithography resist is provided on the nanomaterial. An opening in the at least one layer of resist exposes a surface portion of the nanomaterial. At least a portion of the exposed surface portion of the nanomaterial is removed to thereby expose the underlying substrate and an edge of the nanomaterial. A metal is deposited on at least the edge of the nanomaterial and the exposed substrate such that the metal forms an electrical contact with the nanomaterial. Removing at least a portion of the soluble lithography resist from the nanomaterial such that at least a portion of the two-dimensional material is exposed.

Abstract: Disclosed are approaches for forming semiconductor device cavities using directional dielectric deposition. One method may include providing a plurality of semiconductor structures and a plurality of trenches of a semiconductor device, and forming a dielectric atop the plurality of semiconductor structures by delivering a dielectric material at a non-zero angle of inclination relative to a normal extending perpendicular from a top surface of the plurality of semiconductor structures. The dielectric may be further formed by delivering the dielectric material at a second non-zero angle of inclination relative to the normal extending perpendicular from the top surface of the plurality of semiconductor structures.

Abstract: A display substrate and a display panel are provided. The display substrate includes: a substrate. The display substrate includes a first display region and a second display region. A light transmittance of the first display region is greater than a light transmittance of the second display region. The first display region is provided with a first pixel unit, and the second display region is provided with a second pixel unit, wherein a ratio of a first size of the first pixel unit in a first direction to a second size of the first pixel unit in a second direction is substantially same as a ratio of a first size of the second pixel unit in the first direction to a second size of the second pixel unit in the second direction, the first direction intersecting with the second direction.

Abstract: The present application provides a method for detecting temperature of thermal chamber comprising: conducting a thermal treatment at a predicted temperature to a selected silicon wafer within a thermal chamber, wherein the predicted temperature comprises plural temperature points set in order; obtaining a haze value corresponding to the predicted temperature; obtaining a linear relationship I between the temperature and the haze; polishing and washing the silicon wafer; conducting a thermal treatment at a predicted temperature to the polished silicon wafer within the thermal chamber; obtaining a linear relationship II between the temperature and the haze; calculating a difference of the haze at same temperature point between the two thermal treatments, and obtaining an actual temperature difference of the thermal chamber based on the difference of the haze.

Abstract: A display substrate and a display device. The display substrate includes a display region, a first connecting wire, and a second connecting wire. A first display region includes a first sub-pixel array, including a plurality of light emitting elements arranged in an array, and the plurality of light emitting elements include a first light emitting element and a second light emitting element. The second display region includes a first pixel circuit array, including a plurality of first pixel circuit units, and the plurality of pixel circuit units include a first pixel circuit (D10) and a second pixel circuit. The first connecting wire (151) is connected to the first pixel circuit and the first light emitting element. The second connecting wire is connected to the second pixel circuit and the second light emitting element. The second connecting wire extends in a first direction, the first connecting wire extends in a second direction.

Abstract: Aspects of the present disclosure relate to methods, systems, and apparatus for conducting a radical treatment operation on a substrate prior to conducting an annealing operation on the substrate. In one implementation, a method of processing semiconductor substrates includes pre-heating a substrate, and exposing the substrate to species radicals. The exposing of the substrate to the species radicals includes a treatment temperature that is less than 300 degrees Celsius, a treatment pressure that is less than 1.0 Torr, and a treatment time that is within a range of 8.0 minutes to 12.0 minutes. The method includes annealing the substrate after the exposing of the substrate to the species radicals. The annealing includes exposing the substrate to molecules, an anneal temperature that is 300 degrees Celsius or greater, an anneal pressure that is within a range of 500 Torr to 550 Torr, and an anneal time that is less than 4.0 minutes.

Abstract: Embodiments include a cooling solution having a first array of fins, where the first array of fins extend vertically from the substrate, and where adjacent individual fins of the first array are separated from each other by a microchannel. A second array of fins extend vertically from the substrate, where a channel region is between the first array of fins and the second array of fins.

Abstract: Wafers including a diamond layer and a semiconductor layer having III-Nitride compounds and methods for fabricating the wafers are provided. A nucleation layer, at least one semiconductor layer having III-Nitride compound and a protection layer are formed on a silicon substrate. Then, a silicon carrier wafer is glass bonded to the protection layer. Subsequently the silicon substrate, nucleation layer and a portion of the semiconductor layer are removed. Then, an intermediate layer, a seed layer and a diamond layer are sequentially deposited on the III-Nitride layer. Next, a support wafer that includes a GaN layer (or a silicon layer covered by a protection layer) is deposited on the diamond layer. Then, the silicon carrier wafer and the protection layer are removed.

Abstract: Wafers including a diamond layer and a semiconductor layer having III-Nitride compounds and methods for fabricating the wafers are provided. A nucleation layer, at least one semiconductor layer having III-Nitride compound and a protection layer are formed on a silicon substrate. Then, a silicon carrier wafer is glass bonded to the protection layer. Subsequently the silicon substrate, nucleation layer and a portion of the semiconductor layer are removed. Then, an intermediate layer, a seed layer and a diamond layer are sequentially deposited on the III-Nitride layer. Next, a substrate wafer that includes a glass substrate (or a silicon substrate covered by a protection layer) is glass bonded to the diamond layer. Then, the silicon carrier wafer and the protection layer are removed.

Abstract: Provided is a solid-state image capturing element including a semiconductor substrate and first and second photoelectric conversion parts configured to convert light into electric charge. The first and the second photoelectric conversion parts each have a laminated structure including an upper electrode, a lower electrode, a photoelectric conversion film sandwiched between the upper electrode and the lower electrode, and an accumulation electrode facing the upper electrode through the photoelectric conversion film and an insulating film.

Abstract: Embodiments of the invention provide a method that includes forming an IC layer having an inactive region and an active region. The active region includes a device-under-fabrication (DUF). The inactive region includes a geometric feature having a geometric shape. A film is deposited over the active DUF and the geometric feature such that a first portion of the film will be part of the active DUF, and such that a second portion of the film is over the geometric feature. A geometric shape of the film over the geometric feature matches the geometric shape of the geometric feature. Determining a thickness of the film is based at least in part a difference between a footprint of the geometric shape of the film and a footprint of the geometric shape of the geometric feature.

Abstract: This disclosure describes the structure and technology to modify the free electron density between the gate and drain electrodes of III-nitride semiconductor transistors. Electron density reduction regions (EDR regions) are disposed between the gate and the drain of the transistor structure. In certain embodiments, the EDR regions are created using trenches. In other embodiments, the EDR regions are created by implanting the regions with a species that reduces the free electrons in the channel layer. In another embodiment, the EDR regions are created by forming a cap layer over the barrier layer, wherein the cap layer reduces the free electrons in the channel beneath the cap layer. In another embodiment, a cap layer may be formed in the EDR regions, and doped regions may be created outside of the EDR regions, wherein the impurities act as electron donors.

Abstract: The present disclosure discloses a display panel, a method for preparing the display panel, and a display device. The display panel is divided into a display area and a non-display area. The display panel in the non-display area includes: a substrate; a metal wiring layer arranged on the substrate, the metal wiring layer including metal wirings; a planarization layer covering the substrate and the metal wiring layer, the planarization layer being provided with grooves corresponding to the metal wirings, and the grooves each being located on a side, facing away from the substrate, of a metal wiring corresponding to the each groove and exposing the metal wiring; and a flexible electrode layer filling the grooves, the flexible electrode layer being coupled to the metal wiring layer located at bottoms of the grooves.

Abstract: A method of real time leveling control between a superstrate and a substrate is provided. A contact force model indicating a relationship between a total contact force for planarization of a formable material between the superstrate and the substrate and a force component of the total contact force along each of a plurality peripheral axes is identified. A set point force required for performing the planarization is determined. Each force component is calculated based on the contact force model. The planarization is performed by applying each force component along a corresponding axis of the plurality of axes. The contact force model is identified based on a parallel condition between two contacting surfaces of a superstrate chuck for retaining the superstrate and a stack of the superstrate, the substrate, and formable material between the superstrate and the substrate.

Abstract: Types, sizes, and locations of crystal defects of an epitaxial layer of a semiconductor wafer containing silicon carbide are detected. Next, a predetermined device element structure is formed and based on location information of the crystal defects of the semiconductor wafer, semiconductor chips free of crystal defects and semiconductor chips containing only extended defects (Frank dislocations, carrot defects) are identified as conforming product candidates among individual semiconductor chips cut from the semiconductor wafer while semiconductor chips containing foreign particle defects and triangular defects are removed as non-conforming chips. Next, electrical characteristics of all the semiconductor chips that are conforming product candidates are checked. Next, based on a conforming product standard obtained in advance, a standard judgment is performed for all the semiconductor chips that are conforming product candidates, whereby semiconductor chips that are conforming products are identified.

Abstract: Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures or conductive structures.

Abstract: A terminal includes a substrate and a photosensitive chip mounted on the substrate, where a side of the photosensitive chip away from the substrate has a photosensitive area and a non-photosensitive area surrounding the photosensitive area, and the photosensitive chip is electrically connected to the substrate by using a metal wire; and the photosensitive chip package structure further includes: a frame, disposed on the side of the photosensitive chip away from the substrate, where an avoidance groove used to avoid the metal wire is disposed on a side of the frame facing the substrate, the avoidance groove extends along a side edge of the frame, and an inner wall of the avoidance groove is an arc-shaped inner wall; and a filling glue, filled in the avoidance groove, and used to wrap the metal wire and bond the frame to the non-photosensitive area of the photosensitive chip and the substrate.