Abstract: A terminal includes a substrate and a photosensitive chip mounted on the substrate, where a side of the photosensitive chip away from the substrate has a photosensitive area and a non-photosensitive area surrounding the photosensitive area, and the photosensitive chip is electrically connected to the substrate by using a metal wire; and the photosensitive chip package structure further includes: a frame, disposed on the side of the photosensitive chip away from the substrate, where an avoidance groove used to avoid the metal wire is disposed on a side of the frame facing the substrate, the avoidance groove extends along a side edge of the frame, and an inner wall of the avoidance groove is an arc-shaped inner wall; and a filling glue, filled in the avoidance groove, and used to wrap the metal wire and bond the frame to the non-photosensitive area of the photosensitive chip and the substrate.

Abstract: A display substrate and a display device are disclosed. In the display substrate, a pixel defining layer includes a plurality of opening groups, each of the opening groups includes a first opening and a second opening, the spacer is located between the first opening of a first opening group row and the second opening of a second opening group row, an orthographic projection of the first opening includes a first long edge, and an orthographic projection of the second opening includes a second long edge, an orthographic projection of the spacer includes a third long edge, and an angle between the third long edge and the first long edge ranges from 20 degrees to 70 degrees, the orthographic projection of the first opening includes a first short edge, and the length of the third long edge is greater than that of the first short edge.

Abstract: Disclosed is a semiconductor device and a method for fabricating such semiconductor device, specifically a High Electron Mobility Transistor (HEMT) with a back barrier layer for blocking electron leakage and improve threshold voltage. In one embodiment, a semiconductor device, includes: a Gallium Nitride (GaN) layer; a front barrier layer over the GaN layer; a source electrode, a drain electrode and a gate electrode formed over the front barrier layer; a 2-Dimensional Electron Gas (2-DEG) in the GaN layer at a first interface between the GaN layer and the front barrier layer; and a back barrier layer in the GaN layer, wherein the back barrier layer comprises Aluminum Nitride (AlN).

Abstract: An object of the disclosure is to provide a semiconductor device having enhanced adhesion of the electrode while improving the reverse direction breakdown voltage, which is especially useful for power devices. A semiconductor device including a semiconductor layer and an electrode layer provided on the semiconductor layer and including at least a first electrode layer and a second electrode layer provided on the first electrode layer, wherein an outer edge portion of the second electrode layer is located outside an outer edge portion of the first electrode layer, wherein the semiconductor layer includes an electric field relaxation region with a different electrical resistivity from that of the semiconductor layer, and wherein the electric field relaxation region overlaps at least a part of a portion of the second electrode layer located outside the outer edge portion of the first electrode layer in plan view.

Abstract: There is provided a manufacturing method for a thermal conductive layer, with which a thermal conductive layer having a thermal diffusivity of 3.0×10?7 m2s?1 or more is manufactured on a support by using a composition for forming a thermal conductive layer, the composition containing a resin, a filler, and a solvent and having a concentration of solid contents of less than 90% by mass, the manufacturing method including a discharge step of discharging the composition toward the support; and a solvent amount reduction step of reducing a solvent amount in the composition such that a first solvent amount reduction time taken after the composition is discharged until the concentration of solid contents in the composition reaches 90% by mass on the support is 10 seconds or more for each position on the support.

Abstract: A semiconductor device according to an embodiment includes: a silicon carbide layer; a silicon oxide layer; and a region disposed between the silicon carbide layer and the silicon oxide layer and having a nitrogen concentration equal to or more than 1×1021 cm?3. A nitrogen concentration distribution in the silicon carbide layer, the silicon oxide layer, and the region have a peak in the region, a nitrogen concentration at a first position 1 nm away from the peak to the side of the silicon oxide layer is equal to or less than 1×1018 cm?3 and a carbon concentration at the first position is equal to or less than 1×1018 cm?3, and a nitrogen concentration at a second position 1 nm away from the peak to the side of the silicon carbide layer is equal to or less than 1×1018 cm?3.

Abstract: A semiconductor structure is provided. The semiconductor structure comprises a heat generating device arranged over a substrate. An interlayer dielectric (ILD) material may be arranged over the heat generating device and the substrate. A metallization layer may be arranged over the interlayer dielectric material. A thermal shunt structure may be arranged proximal the heat generating device, whereby an upper portion of the thermal shunt structure may be arranged in the interlayer dielectric material and may be lower than the metallization layer, and a lower portion of the thermal shunt structure may be arranged in the substrate.

Abstract: To provide a nitride semiconductor device excellent in switching characteristics. A nitride semiconductor device includes: a gallium nitride layer having a first principal surface and a second principal surface located on an opposite side to the first principal surface and having a trench formed from the first principal surface to the second principal surface side; and a field effect transistor formed in the gallium nitride layer, wherein the trench has a first side surface and a second side surface inside the trench, the first side surface is a nitrogen face in the surface layer of which nitrogen atoms are located, the second side surface is a gallium face in the surface layer of which gallium atoms are located, and the field effect transistor has: a gate insulating film formed on the first side surface; and a gate electrode formed in the trench and covering the gate insulating film.

Abstract: A method of real time leveling control between a superstrate and a substrate is provided. A contact force model indicating a relationship between a total contact force for planarization of a formable material between the superstrate and the substrate and a force component of the total contact force along each of a plurality peripheral axes is identified. A set point force required for performing the planarization is determined. Each force component is calculated based on the contact force model. The planarization is performed by applying each force component along a corresponding axis of the plurality of axes. The contact force model is identified based on a parallel condition between two contacting surfaces of a superstrate chuck for retaining the superstrate and a stack of the superstrate, the substrate, and formable material between the superstrate and the substrate.

Abstract: A device including a gate stack over a semiconductor substrate having a pair of spacers abutting sidewalls of the gate stack. A recess is formed in the semiconductor substrate adjacent the gate stack. The recess has a first profile having substantially vertical sidewalls and a second profile contiguous with and below the first profile. The first and second profiles provide a bottle-neck shaped profile of the recess in the semiconductor substrate, the second profile having a greater width within the semiconductor substrate than the first profile. The recess is filled with a semiconductor material. A pair of spacers are disposed overly the semiconductor substrate adjacent the recess.

Abstract: The present disclosure relates to a reflective electrode and an array substrate and a display device thereof. The reflective electrode includes a reflective conductive layer and a color compensation layer located on the reflective conductive layer. The reflective conductive layer has a first reflectivity to first light having a first wavelength and a second reflectivity to second light having a second wavelength. The first light and the second light are combined into white light. The first reflectivity is smaller than the second reflectivity. The color compensation layer is configured such that the reflective electrode has a third reflectivity to the first light and a fourth reflectivity to the second light. A ratio of an absolute value of a difference between the third reflectivity and the fourth reflectivity to the third reflectivity is smaller than 16.4%.

Abstract: A semiconductor device is provided, including: a substrate; and a first semiconductor layer including magnesium and Alx/Ga1?x1N (0?x1<1), the first semiconductor layer including a first region, a second region, and a third region, the first region being between the substrate and the third region, the second region being between the first region and the third region, a first concentration of magnesium in the first region being greater than a third concentration of magnesium in the third region, a second concentration of magnesium in the second region decreasing along a first orientation, the first orientation being from the substrate toward the first semiconductor layer, and the first region not including carbon, or a concentration of carbon in the first region being less than the concentration of carbon in the third region.

Abstract: A method for activating implanted dopants and repairing damage to dopant-implanted GaN to form n-type or p-type GaN. A GaN substrate is implanted with n- or p-type ions and is subjected to a high-temperature anneal to activate the implanted dopants and to produce planar n- or p-type doped areas within the GaN having an activated dopant concentration of about 1018-1022 cm?3. An initial annealing at a temperature at which the GaN is stable at a predetermined process temperature for a predetermined time can be conducted before the high-temperature anneal. A thermally stable cap can be applied to the GaN substrate to suppress nitrogen evolution from the GaN surface during the high-temperature annealing step. The high-temperature annealing can be conducted under N2 pressure to increase the stability of the GaN. The annealing can be conducted using laser annealing or rapid thermal annealing (RTA).

Abstract: A semiconductor structure and a forming method thereof are provided.

Abstract: A method of making a semiconductor device includes depositing an amorphous layer on a substrate, masking a portion of the amorphous layer, removing a portion of the amorphous layer to form a first channel into the amorphous layer, depositing a semiconductor layer onto the substrate layer, and removing at least a portion of a defect region of the semiconductor layer to form a second channel.

Abstract: A method of fabricating a semiconductor package includes preparing a panel package including a redistribution substrate, a connection substrate and a plurality of lower semiconductor chips; sawing the panel package to form a plurality of separated strip packages each of which includes the sawed redistribution substrate, at least two of the lower semiconductor chips, and the sawed connection substrate; and providing a plurality of upper semiconductor chips on one of the strip packages to electrically connect the upper semiconductor chips to the sawed connection substrate.

Abstract: A method for forming a chip package structure is provided. The method includes disposing a chip package over a wiring substrate. The method includes forming a first heat conductive structure and a second heat conductive structure over the chip package. The first heat conductive structure and the second heat conductive structure are separated by a first gap. The method includes bonding a heat dissipation lid to the chip package through the first heat conductive structure and the second heat conductive structure. The first heat conductive structure and the second heat conductive structure extend toward each other until the first heat conductive structure contacts the second heat conductive structure during bonding the heat dissipation lid to the chip package.

Abstract: A semiconductor memory device includes word lines extending in a first direction on a semiconductor substrate, bit line structures crossing over the word lines and extending in a second direction intersecting the first direction, and contact pad structures between the word lines and between the bit line structures in plan view. A spacer structure extends between the bit line structures and the contact pad structures. The spacer structure includes a first air gap extending in the second direction along sidewalls of the bit line structures and a second air gap surrounding each of the contact pad structures and coupled to the first air gap.

Abstract: A method of transferring micro-devices includes selectively treating a first adhesive layer to form a treated portion and an untreated portion while micro-devices are attached the first adhesive layer. A second adhesive layer on a second surface is placed to abut the micro-devices. The first adhesive layer is exposed to illumination in a region that overlaps at least some of the treated portion and at least some of the untreated portion. Exposing the first adhesive layer to illumination neutralizes the at least some of the untreated portion to create a neutralized portion that is less adhesive than an exposed area of the treated portion. The first surface is separated from the second surface such that micro-devices in the treated portion remain attached to the first surface and micro-devices in the neutralized portion are attached to the second surface and separate from the first surface.

Abstract: This semiconductor device according to an embodiment includes: a silicon carbide layer; a gate electrode; a silicon oxide layer between the silicon carbide layer and the gate electrode; and a region between the silicon carbide layer and the silicon oxide layer and having a nitrogen concentration not less than 1×1021 cm?3. A nitrogen concentration distribution in the silicon carbide layer, the silicon oxide layer, and the region has its peak in the region, and a state density Z1/2 in a portion is not more than 1×1011 cm?3. The portion is within 100 nm from the silicon oxide layer toward the silicon carbide layer. A nitrogen concentration and a carbon concentration in a position 1 nm from the peak toward the silicon oxide layer is not more than 1×1018 cm?3, and a nitrogen concentration in a position 1 nm from the peak toward the silicon carbide layer is not more than 1×1018 cm?3.