Abstract: A method for garbage collection in a NAND flash memory system is disclosed. The method includes the steps of receiving a data request task in the NAND flash memory system; executing the data request task in the NAND flash memory system; based on the condition where the number of free data pages in the NAND flash memory system is below the first pre-determined threshold, determining whether a data block partial garbage collection list is empty; based on the condition where the data block partial garbage collection list is empty, selecting a victim block in the NAND flash memory system; and creating a plurality of data block partial garbage collection tasks.

Abstract: A device for interleaving/deinterleaving digital data delivered by processing elements (P0 . . . Pn-1) suitable for being used both with turbo-codes and with LDPC codes. The device includes memory banks (B0 . . . Bm-1) for storing data coming from or going to the processing elements, an interconnection network (INT) for directing the data between the processing elements and the memory banks, and a control unit (CTRL) for controlling the interconnection network and the memory banks. The control unit (CTRL) includes a calculation circuit (CAL) capable of the online generation of command words for the interconnection network and addressing and control sequences of the memory banks, ensuring conflict-free memory access on the basis of the interleaving rule to be applied, the size of the digital data frames, the number of processing units and memory banks, and the interconnection network.

Abstract: Methods of accessing memory cells, methods of distributing memory requests, systems, and memory controllers are described. In one such method, where memory cells are divided into at least a first region of memory cells and a second region of memory cells, memory cells in the first region are accessed according to a first address definition and memory cells in the second region are accessed according to a second address definition that is different from the first address definition. Additional embodiments are described.

Abstract: A memory module stores memory access metadata reflecting information about memory accesses to the memory module. The memory access metadata can indicate the number of times a particular unit of data (e.g., a row of data, a unit of data corresponding to a cache line, and the like) has been read, written, had one or more of its bits flipped, and the like. Modifications to the embedded access metadata can be made by a control module at the memory module itself, thereby reducing overhead at a processor core. In addition, the control module can be configured to record different access metadata for different memory locations of the memory module.

Abstract: The various implementations described herein include systems, methods and/or devices used to enable multi-phase erasure in a storage device. The method includes performing an erase operation on a portion of one or more non-volatile memory devices, by performing a sequence of erase phase operations until an erase operation stop condition is satisfied. Each erase phase operation includes: performing an erase phase on the portion of the non-volatile memory devices using an erase voltage, and determining an erase phase statistic for the erase phase. For each erase phase operation in the sequence of erase phase operations, other than a first erase phase operation, the erase voltage used when performing the erase phase operation is equal to the erase voltage used when performing a prior erase phase operation in the sequence of erase phase operations plus an erase voltage increment based on the erase phase statistic for the prior erase phase operation.

Abstract: A multi-core processor includes a plurality of cores to execute a plurality of threads and to monitor metrics for each of the plurality of threads during an interval, the metrics including stall cycle values, prefetches of a first type, and prefetches of a second type. The multi-core processor further includes criticality-aware thread prioritization (CATP) logic to compute a stall fraction for each of the plurality of threads during the interval using the stall cycle values, identify a thread with a highest stall fraction of the plurality of threads, determine the highest stall fraction is greater than a stall threshold, prioritize demand requests of the identified thread, compute a prefetch accuracy of the identified thread during the interval using the prefetches of the first type and the prefetches of the second type, determine the prefetch accuracy is greater than a prefetch threshold, and prioritize prefetch requests of the identified thread.

Abstract: On-chip instruction RAM is leveraged as an extension of on-chip data RAM during normal use of a modified Harvard Architecture processor. Unused space in an instruction RAM is detected in a modified Harvard Architecture processor. During operation of the processor this unused space is used to load and store data normally loaded and stored in an on-chip data RAM. A performance penalty associated with swapping out to external memory is reduced. The type of data stored in the unused portion of the instruction RAM may be selected to optimize performance. In one implementation, the unused space in the instruction RAM is used to load and store only a single type of data, such as heap, stack, initialized or uninitialized data.

Abstract: In dynamic data access, a request is received to access data of a core data service view of an in-memory database. It is determined that an aging temperature parameter is specified in an annotation in a core data service view definition. An aging temperature value corresponding to the aging temperature parameter is received as a range restriction. A default access behavior associated with the core data service view definition is overridden. A partition where the aging temperature value lies in a secondary memory is determined. Latest or recent partition in the secondary memory is referred to as a latest partition. Data from the latest partition until the determined partition is accessed in the secondary memory. The accessed data is loaded from the secondary memory to the main memory.

Abstract: Systems, methods, and/or devices are used to implement variable bit encoding to improve device endurance and extend life of storage devices. In some embodiments, the method includes determining a current endurance metric for a plurality of non-volatile memory portions configured to store data encoded in a first encoding format and determining an estimated endurance metric for the plurality of non-volatile memory portions (e.g., corresponding to estimated endurance after reconfiguration of the one or more portions to store data encoded in a second encoding format), and in accordance with a determination that reconfiguration criteria are satisfied (e.g., the estimated endurance metric comprises an improvement over the current endurance metric), reconfiguring the one or more portions to store data encoded in the second encoding format.

Abstract: Example devices are disclosed. For example, a device may include a processor, a plurality of translation lookaside buffers, a plurality of switches, and a memory management unit. Each of the translation lookaside buffers may be assigned to a different process of the processor, each of the plurality of switches may include a register for storing a different process identifier, and each of the plurality of switches may be associated with a different one of the translation lookaside buffer buffers. The memory management unit may be for receiving a virtual memory address and a process identifier from the processor and forwarding the process identifier to the plurality of switches. Each of the plurality of switches may be for connecting the memory management unit to a translation associated with the switch when there is a match between the process identifier and the different process identifier stored by the register of the switch.

Abstract: A processor-based method for flash-friendly caching is provided. The method includes reading data from a first memory and writing the data to a second memory, in a cache. The method includes performing an aligned block write of data from the second memory in the cache to a flash memory in the cache, responsive to accumulating sufficient data for the aligned block write.

Abstract: According to an embodiment, when data read from a first storage unit which is a backup source is not identical with data indicated by a first function, the read data is written to a second storage unit which is a backup destination. When the data read from the first storage unit is identical with the data indicated by the first function, the read data is not written to the second storage unit and a deletion notification is sent to the second storage unit.

Abstract: A medical device system includes a first medical device, a first memory corresponding to the first medical device, a second medical device, and a second memory corresponding to the second medical device, wherein the first medical device includes a first writing unit that dynamically writes, into an area included in the first memory, definition data that defines a method for using the area and data corresponding to the definition data, and the second medical device includes a second writing unit that dynamically writes, into an area included in the second memory, definition data that defines a method for using the area and data corresponding to the definition data.

Abstract: Apparatuses and methods for determining soft data for fractional digit memory cells are provided. One example apparatus can include a controller to determine states of memory cells of a group of memory cells operated as fractional digit memory cells, and determine soft data based, at least partially, on dimensions to which particular memory cells correspond with respect to the group of memory cells, determined states of the memory cells with respect to a state adjacent a state corresponding to a swapping shell, and whether a particular memory cell is a candidate for swapping.

Abstract: Systems, methods, and/or devices are used to implement variable bit encoding per NAND flash cell to extend life of flash-based storage devices and preserve over-provisioning. In some embodiments, the method includes detecting a trigger condition with respect to one or more non-volatile memory portions (e.g., portions configured to store data encoded in a first encoding format and having a first storage density) of a plurality of non-volatile memory portions of a storage device. In response to detecting the trigger condition and in accordance with a first determination that a projected amount of over-provisioning (e.g., corresponding to over-provisioning for the storage device after reconfiguring the one or more non-volatile memory portions to store data encoded in a second encoding format and having a second storage density) meets predefined over-provisioning criteria, the method includes reconfiguring the one or more non-volatile memory portions to store data encoded in the second encoding format.

Abstract: A peer to peer remote copy operation is performed between a primary storage controller and a secondary storage controller, to establish a peer to peer remote copy relationship between a primary storage volume and a secondary storage volume. Subsequent to indicating completion of the peer to peer remote copy operation to a host, a determination is made as to whether the primary storage volume and the secondary storage volume have identical data, by performing operations of staging data of the primary storage volume from auxiliary storage of the primary storage controller to local storage of the primary storage controller, and transmitting the data of the primary storage volume that is staged, to the secondary storage controller for comparison with data of the secondary storage volume stored in an auxiliary storage of the secondary storage controller.

Abstract: A memory controller issues a targeted refresh command. A specific row of a memory device can be the target of repeated accesses. When the row is accessed repeatedly within a time threshold (also referred to as “hammered” or a “row hammer event”), physically adjacent row (a “victim” row) may experience data corruption. The memory controller receives an indication of a row hammer event, identifies the row associated with the row hammer event, and sends one or more commands to the memory device to cause the memory device to perform a targeted refresh that will refresh the victim row.

Abstract: An electronic system includes: a master controller configured to: monitor an execution of a user program, and generate a pre-fetching hint; a cluster node, coupled to the master controller, configured to be a pre-processing client; a local storage, coupled to the cluster node, configured to store input data for the user program; and wherein the master controller is further configured to: transfer the pre-fetching hint to the pre-processing clients for pre-fetching a split of the input data from the local storage based on the pre-fetching hint.

Abstract: A processor includes a processing core, an L1 cache, operatively coupled to the processing core, the L1 cache comprising an L1 cache entry to store a data item, an L2 cache, inclusive with respect to the L1 cache, the L2 cache comprising an L2 cache entry corresponding to the L1 cache entry, an activity flag associated with the L2 cache entry, the activity flag indicating an activity status of the L1 cache entry, and a cache controller to, in response to detecting an access operation with respect to the L1 cache entry, set the flag to an active status.

Abstract: A method, system, and computer-readable medium for evicting cache lines that includes determining that a first cache line is to be evicted from a first Last Level Cache (LLC) partition of a partitioned LLC, and sending, based on the determination, a first notification to a second LLC partition of the partitioned LLC. The method may also include receiving, in response to the first notification, an available indication indicating that the second LLC partition is available as a designated victim cache partition; performing a selection of the second LLC partition as the designated victim cache partition; and evicting the first cache line to the second LLC partition based on the selection.