Patents Examined by Jae Yu
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Patent number: 9483349Abstract: In one embodiment, a node of a cluster having a plurality of nodes, executes a storage input/output (I/O) stack having a redundant array of independent disks (RAID) layer. The RAID layer organizes solid state drives (SSDs) within one or more storage arrays as a plurality of RAID groups associated with one or more extent stores. The RAID groups are formed from slices of storage spaces of the SSDs instead of entire storage spaces of the SSDs. This provides for RAID groups to co-exist on a same set of the SSDs.Type: GrantFiled: January 17, 2014Date of Patent: November 1, 2016Assignee: NetApp, Inc.Inventors: Rajesh Sundaram, Bharat Baddepudi, Jeffrey S. Kimmel
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Patent number: 9471253Abstract: For data processing in a computing storage environment by a processor device, the computing storage environment incorporating at least high-speed and lower-speed caches, and tiered levels of storage, and at a time in which at least one data segment is to be migrated from one level to another level of the tiered levels of storage, a data migration mechanism is initiated by copying data resident in the lower-speed cache corresponding to the at least one data segment to be migrated to a target on the another level, reading remaining data, not previously copied from the lower-speed cache, from a source on the one level, and writing the remaining data to the target, and subsequent to the reading and the writing of the remaining data, destaging updates corresponding to the at least one data segment from either the higher and lower speed caches to the target.Type: GrantFiled: February 4, 2016Date of Patent: October 18, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael T Benhase, Lokesh M. Gupta
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Patent number: 9471229Abstract: Methods and structure for predictively caching data to service host write requests. One embodiment includes a Redundant Array of Independent Disks (RAID) storage controller able to manage a RAID volume implemented on a plurality of storage devices. The storage controller includes a memory able to store a queue of write requests that are directed to the RAID volume, and an Input/Output (I/O) processor. The I/O processor is able to detect a stream of write requests in the queue that are directed to a sequence of Logical Block Addresses (LBAs) at the RAID volume, to predict, based on the stream, LBAs for new write requests, to cache data for the predicted LBAs from the storage devices to the storage controller, to receive the new write requests, and to utilize the cached data from the predicted LBAs to generate parity data for the new write requests.Type: GrantFiled: December 15, 2014Date of Patent: October 18, 2016Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.Inventors: Vinu Velayudhan, Varadaraj S. Talamacki
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Patent number: 9471252Abstract: For data processing in a computing storage environment by a processor device, the computing storage environment incorporating at least high-speed and lower-speed caches, and tiered levels of storage, and at a time in which at least one data segment is to be migrated from one level to another level of the tiered levels of storage, a data migration mechanism is initiated by copying data resident in the lower-speed cache corresponding to the at least one data segment to be migrated to a target on the another level, reading remaining data, not previously copied from the lower-speed cache, from a source on the one level, and writing the remaining data to the target, and subsequent to the reading and the writing of the remaining data, destaging updates corresponding to the at least one data segment from either the higher and lower speed caches to the target.Type: GrantFiled: February 4, 2016Date of Patent: October 18, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael T. Benhase, Lokesh M. Gupta
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Patent number: 9471506Abstract: For data processing in a computing storage environment by a processor device, the environment incorporating at least high-speed and lower-speed caches, and managed tiered levels of storage, groups of data segments are migrated between the tiered levels of storage such that clumped uniformly hot ones of the groups of data segments are migrated to use a Solid State Drive (SSD) portion of the tiered levels of storage; uniformly hot groups of data segments are determined using a first, largest granulated, heat map for a selected one of the group of the data segments; a second heat map, which is smaller than the first and having the largest granularity of the first heat map, is used to determine the clumped hot groups; and sparsely hot groups are determined when neither the first heat map nor the second heat map are hotter than the first and second predetermined thresholds, respectively.Type: GrantFiled: April 22, 2015Date of Patent: October 18, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael T. Benhase, Lokesh M. Gupta, Cheng-Chung Song
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Patent number: 9465554Abstract: For data processing in a distributed computing storage environment by a processor device, the distributed computing environment incorporating at least high-speed and lower-speed caches, and managed tiered levels of storage, groups of data segments and clumped hot ones of the data segments are migrated between the tiered levels of storage such that uniformly hot ones of the groups of data segments are migrated to use a Solid State Drive (SSD) portion of the tiered levels of storage; uniformly hot groups of data segments are determined using a first, heat map for a selected one of the group of the data segments; and a second heat map is used to determine the clumped hot groups.Type: GrantFiled: January 18, 2016Date of Patent: October 11, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael T. Benhase, Lokesh M. Gupta, Cheng-Chung Song
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Patent number: 9466344Abstract: A system and method for decoding command signals that includes a command decoder configured to generate internal control signals to perform an operation based on the command signals and an operating state. The same combination of command signals can request different commands depending on the operating state. A command is selected from a first set of operations according to the command signals when the memory system is in a first operating state and a command is selected from a second set of operations according to the command signals when the memory system is in a second operating state.Type: GrantFiled: June 5, 2012Date of Patent: October 11, 2016Assignee: Micron Technology, Inc.Inventors: Jeffery W. Janzen, Brent Keeth, Jeffrey P. Wright, James S. Cullum
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Patent number: 9454491Abstract: Systems and methods for accessing a unified translation lookaside buffer (TLB) are disclosed. A method includes receiving an indicator of a level one translation lookaside buffer (L1TLB) miss corresponding to a request for a virtual address to physical address translation, searching a cache that includes virtual addresses and page sizes that correspond to translation table entries (TTEs) that have been evicted from the L1TLB, where a page size is identified, and searching a second level TLB and identifying a physical address that is contained in the second level TLB. Access is provided to the identified physical address.Type: GrantFiled: January 6, 2015Date of Patent: September 27, 2016Assignee: SOFT MACHINES INC.Inventors: Karthikeyan Avudaiyappan, Mohammad Abdallah
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Patent number: 9448929Abstract: A computer-implemented method for compilation of applications can include receiving a set of software instructions and traversing the set of software instructions based on a control-flow order of the set of software instructions. The traversing can include identifying a first allocation instruction in the set of software instructions, the first allocation instruction being configured to allocate a first amount of memory for a first object and identifying a second allocation instruction in the set of software instructions, the second allocation instruction being configured to allocate a second amount of memory for a second object. The method can include determining that the first allocation instruction dominates the second allocation instruction and, in response to the determining, combining the first allocation instruction and the second allocation instruction into a folded allocation instruction that allocates the first amount of memory and the second amount of memory in a single memory allocation operation.Type: GrantFiled: July 10, 2014Date of Patent: September 20, 2016Assignee: Google Inc.Inventors: Hannes Payer, Daniel Kenneth Clifford, Ben Titzer, Michael Starzinger
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Patent number: 9436597Abstract: A buffer pool for a database application is maintained in a volatile main memory component. A control portion that corresponds to a block of application data residing on a non-volatile, asymmetric memory component and that includes a reference to a location of the block of application data on the non-volatile, asymmetric memory component is added to the buffer pool maintained in the volatile main memory component. The control portion from the buffer pool maintained in the volatile main memory component that corresponds to the block of application data is accessed and the location of the block of application data on the non-volatile, asymmetric memory component is identified. Based on identifying the location of the block of application data on the non-volatile, asymmetric memory component, the database application is enabled to access the block of application data directly from the non-volatile, asymmetric memory component.Type: GrantFiled: July 1, 2013Date of Patent: September 6, 2016Assignee: Virident Systems Inc.Inventor: Vijay Karamcheti
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Patent number: 9430276Abstract: A transactional memory system coalesces two outermost transactions in a transactional memory environment. A processor of the transactional memory system executes a first transaction begin instruction of a first outermost transaction and processes the first transaction. Based on encountering a first transaction end instruction of the first outermost transaction, the processor determines whether the first transaction is to-be coalesced with a second outermost transaction.Type: GrantFiled: June 15, 2015Date of Patent: August 30, 2016Assignee: International Business Machines CorporationInventors: Fadi Y. Busaba, Michael Karl Gschwind, Maged M. Michael, Valentina Salapura, Chung-Lung K. Shum
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Patent number: 9430404Abstract: For data processing in a computing storage environment by a processor device, the computing storage environment incorporating at least high-speed and lower-speed caches, and managed tiered levels of storage, a Solid State Device (SSD) tier is variably shared between the lower-speed cache and the managed tiered levels of storage such that the managed tiered levels of storage are operational on large data segments, and the lower-speed cache is allocated with the large data segments, yet operates with data segments of a smaller size than the large data segments and within the large data segments, where if selected data segments are cached in the lower-speed cache and are determined to become uniformly hot, the selected group from the lower-speed cache are migrated to the SSD tier.Type: GrantFiled: August 11, 2015Date of Patent: August 30, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael T. Benhase, Lokesh M. Gupta, Karl A. Nielsen
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Patent number: 9411716Abstract: System and method for automated page-based management in storage systems. The system includes host computers, file servers and a storage system having automated page-based management means. The storage system interface receives instructions to change the condition for decision for migration regarding particular parts or the whole volume. The host computer can control execution of the migration performed by the storage system by specifying areas or volumes with the condition via the interface. Highly optimized, appropriate data placement and data relocation in computer system can be achieved when the application, host computer or management computer can recognize or predict the usage of the data or files. The storage system having automated page-based management may include compression/decompression and a control method for the compression and decompression process.Type: GrantFiled: February 7, 2014Date of Patent: August 9, 2016Assignee: Hitachi, Ltd.Inventor: Hiroshi Arakawa
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Patent number: 9411742Abstract: For data processing in a computing storage environment by a processor device, the computing storage environment incorporating at least high-speed and lower-speed caches, and tiered levels of storage, groups of data segments are migrated between the tiered levels of storage such that if a selected group is cached in the lower-speed cache and is determined to become uniformly hot, migrating the selected group from the lower-speed cache to the SSD portion while refraining from processing data retained in the lower-speed cache until the selected group is fully migrated to the SSD portion.Type: GrantFiled: October 5, 2015Date of Patent: August 9, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael T. Benhase, Lokesh M. Gupta, Cheng-Chung Song
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Patent number: 9405693Abstract: In order to provide a more efficient persistent storage device, one or more long-term storage media are included along with a non-volatile memory. In one embodiment, one portion of the non-volatile memory is used as a write buffer and a read cache for writes and reads to the long-term storage media. Interfaces are provided for controlling the use of the non-volatile memory as a write buffer and a read cache. Additionally, a portion of the non-volatile memory is used to provide a direct mapping for specified sectors of the long-term storage media. Descriptive data regarding the persistent storage device is stored in another portion of the non-volatile memory.Type: GrantFiled: July 23, 2012Date of Patent: August 2, 2016Assignee: Microsoft Technology Licensing, LLCInventors: Cenk Ergan, Clark D. Nicholson, Daniel Teodosiu, Dean L. DeWhitt, Emily Nicole Hill, Hanumantha R. Kodavalla, Michael J. Zwilling, John M. Parchem, Michael R. Fortin, Nathan Steven Obr, Rajeev Y. Nagar, Surenda Verma, Therron Powell, William J. Westerinen, Mark Joseph Zbikowski, Patrick L. Stemen
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Patent number: 9389789Abstract: As disclosed herein, a method, executed by a computer, for migrating executing applications and associated stored data includes executing one or more applications in a source system environment that access data stored on a source storage device that is directly accessible within the source system environment, migrating the data to a target storage device that is directly accessible within a target system environment but is not directly accessible within the source system environment, wherein migrating the data comprises copying the data from the source storage device to the target storage device using a remote storage access protocol. A computer system and computer program product corresponding to the method are also disclosed herein.Type: GrantFiled: December 15, 2014Date of Patent: July 12, 2016Assignee: International Business Machines CorporationInventor: Gerald F. McBrearty
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Patent number: 9392058Abstract: As disclosed herein, a method, executed by a computer, for migrating executing applications and associated stored data includes executing one or more applications in a source system environment that access data stored on a source storage device that is directly accessible within the source system environment, migrating the data to a target storage device that is directly accessible within a target system environment but is not directly accessible within the source system environment, wherein migrating the data comprises copying the data from the source storage device to the target storage device using a remote storage access protocol. A computer system and computer program product corresponding to the method are also disclosed herein.Type: GrantFiled: June 3, 2015Date of Patent: July 12, 2016Assignee: International Business Machines CorporationInventor: Gerald F. McBrearty
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Patent number: 9383930Abstract: A transactional memory system controls the coalescing of outermost memory transactions. The coalescing causing committing of memory store data to memory for a first transaction to be done at transaction execution (TX) end of a second transaction. A processor of the transactional memory system executes a run-time instrumentation program for monitoring and modifying an associated program having a plurality of transactions. The processor initiates execution of the associated program. Based on execution of transactions, by the processor, of the associated program, the run-time instrumentation program dynamically obtains instrumentation information associated with the execution. Based on the obtained instrumentation information, the processor dynamically modifies continued execution of transactions of the associated program to optimize transactional execution (TX).Type: GrantFiled: September 15, 2015Date of Patent: July 5, 2016Assignee: International Business Machines CorporationInventors: Fadi Y. Busaba, Michael Karl Gschwind, Maged M. Michael, Valentina Salapura, Chung-Lung K. Shum
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Patent number: 9372630Abstract: A method, for migrating newly allocated data into a second storage tier, includes receiving a request to store a data item. The method includes allocating an extent to a first storage tier to store the new data item. The method includes determining whether an extent is newly allocated on the first storage tier. The method includes migrating, by avoiding a learning phase, the newly allocated extent to the second storage tier from the first storage tier.Type: GrantFiled: July 9, 2014Date of Patent: June 21, 2016Assignee: International Business Machines CorporationInventors: Yong Guo, Bruce McNutt, Tao Tang, Yan Xu
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Patent number: 9361031Abstract: A transactional memory system that utilizes indications for the coalescing of outermost memory transactions, the coalescing causing committing of memory store data to memory for a first transaction to be done at transaction execution (TX) end of a second transaction a processor of the transactional memory system executes one or more coalescing instructions for controlling coalescing of a plurality of outermost transactions. Based on the execution of the one or more coalescing instructions, the processor determines whether two outermost transactions are to be coalesced. Based on determining that two outermost transactions are to be coalesced, the processor coalesces at least two outermost transactions included in the plurality of outermost transactions.Type: GrantFiled: September 15, 2015Date of Patent: June 7, 2016Assignee: International Business Machines CorporationInventors: Fadi Y. Busaba, Michael Karl Gschwind, Valentina Salapura, Chung-Lung K. Shum