Abstract: The present disclosure provides a method for preparing a semiconductor device with air spacer for decreasing electrical coupling. The method comprises: forming a plurality of composite pillars over a substrate, wherein the composite pillars include conductive pillars and dielectric caps over the conductive pillars; transforming a sidewall portion of the conductive pillar into a first transformed portion; removing the first transformed portion such that a width of the dielectric cap is greater than a width of a remaining portion of the conductive pillar; forming a supporting pillar between adjacent two of the plurality of composite pillars; and forming a sealing layer at least contacts a top portion of the supporting pillar and a top of the dielectric cap, and air spacers are formed between the sealing layer, the supporting pillar and the remaining portions of the conductive pillars.

Abstract: A method for preparing an array substrate, a display panel and an evaporation apparatus are disclosed. A method comprises: fixing a base substrate to an evaporation stage; attaching at least one shielding sheet to the base substrate to cover at least a preset area of the base substrate; arranging and aligning an open mask in association with the base substrate, wherein the open mask has at least one opening for vapor deposition, and the at least one shielding sheet is positioned corresponding to the at least one opening and each has an area that is less than an area of a corresponding opening to shield a portion of the corresponding opening, and wherein the portion of the corresponding opening is separate from a boundary of the corresponding opening; and evaporating to form an evaporation material layer on the base substrate, to which the shielding sheet is attached.

Abstract: A semiconductor structure includes a substrate, a plurality of conductive features disposed over the substrate, and an isolation structure between conductive features and separating the conductive features from each other. Each of the conductive features includes a first metal layer and a 2D material layer. Another semiconductor structure includes a first conductive feature, a dielectric structure over the first conductive feature, a second conductive feature in the dielectric structure and coupled to the first conductive feature, and a conductive line over and coupled to the second conductive feature. In some embodiments, the conductive line includes a first 3D material layer, a first 2D material layer, and a second 3D material layer. The first 2D material layer is disposed between the first 3D material layer and the second 3D material layer.

Abstract: A superconducting article includes a substrate and a superconducting metal oxide film formed on the substrate. The metal oxide film including ions of an alkali metal, ions of a transition metal, and ions of an alkaline earth metal or a rare earth metal. For instance, the metal oxide film can include Rb ions, La ions, and Cu ions. The superconducting metal oxide film can have a critical temperature for onset of superconductivity of greater than 250 K, e.g., greater than room temperature.

Abstract: An interconnection structure, along with methods of forming such, are described. The structure includes a first conductive feature having a first thickness, a first dielectric material disposed adjacent the first conductive feature, and the first dielectric material has a second thickness greater than the first thickness. The structure further includes a second conductive feature disposed adjacent the first dielectric material, a first etch stop layer disposed on the first conductive feature, a second etch stop layer disposed on the first dielectric material, and a second dielectric material disposed on the first etch stop layer and the second etch stop layer. The second dielectric material is in contact with the first dielectric material.

Abstract: Embedded packaging for high voltage, high temperature operation of power semiconductor devices is disclosed, wherein a semiconductor die is embedded in a dielectric body comprising a dielectric polymer composition characterized by a conductivity transition temperature Tc, a first activation energy EaLow for conduction in a temperature range below Tc, and a second activation energy EaHigh for conduction in a temperature range above Tc. A test methodology is disclosed for selecting a dielectric epoxy composition having values of Tc, EaLow, and EaHigh that provide a conduction value below a required reliability threshold, e.g. ?5×10?13 S/cm, for a specified operating voltage and temperature. For example, the power semiconductor device comprises a GaN HEMT rated for operation at ?100V wherein the package body is formed from a laminated dielectric epoxy composition for operation at >150 C, wherein Tc is ?75 C, EaLow is ?0.

Abstract: Semiconductor structures and method of forming the same are provided. A semiconductor structure according to the present disclosure includes a contact feature in a dielectric layer, a passivation structure over the dielectric layer, a conductive feature over the passivation structure, a seed layer disposed between the conductive feature and the passivation structure, a protecting layer disposed along sidewalls of the conductive feature, and a passivation layer over the conductive feature and the protecting layer.

Abstract: A low-resistance thick-wire integrated inductor may be formed in an integrated circuit (IC) device. The integrated inductor may include an elongated inductor wire defined by a metal layer stack including an upper metal layer, middle metal layer, and lower metal layer. The lower metal layer may be formed in a top copper interconnect layer, the upper metal layer may be formed in an aluminum bond pad layer, and the middle metal layer may comprise a copper tub region formed between the aluminum upper layer and copper lower layer. The wide copper region defining the middle layer of the metal layer stack may be formed concurrently with copper vias of interconnect structures in the IC device, e.g., by filling respective openings using copper electrochemical plating or other bottom-up fill process. The elongated inductor wire may be shaped in a spiral or other symmetrical or non-symmetrical shape.

Abstract: A method used in forming a memory array comprises forming a stack comprising vertically-alternating first tiers and second tiers. First insulator material is above the stack. The first insulator material comprises at least one of (a) and (b), where (a): silicon, nitrogen, and one or more of carbon, oxygen, boron, and phosphorus, and (b): silicon carbide. Channel-material strings are in and upwardly project from an uppermost material that is directly above the stack. Conducting material is directly against laterally-inner sides of individual of the upwardly-projecting channel-material strings and project upwardly from the individual upwardly-projecting channel-material strings. A ring comprising insulating material is formed individually circumferentially about the upwardly-projecting conducting material. Second insulator material is formed above the first insulator material, the ring, and the upwardly-projecting conducting material.

Abstract: The present application discloses a display substrate. The display substrate may include a base substrate; a plurality of first electrodes arranged in an array on the base substrate; and a pixel defining layer defining a plurality of openings on the base substrate. The plurality of openings may overlap the plurality of first electrodes respectively. The pixel defining layer may include a plurality of first pixel defining units and a plurality of second pixel defining units; and the plurality of first pixel defining units may be separated from one another.

Abstract: A semiconductor device includes a first semiconductor chip that includes a first conductive pad whose top surface is exposed; and a second semiconductor chip that includes a second conductive pad whose top surface is exposed and in contact with at least a portion of the top surface of the first conductive pad. The first semiconductor chip may include a first diffusion barrier in contact with a bottom surface of the first conductive pad, and a second diffusion barrier in contact with a lateral surface of the first conductive pad, and the first diffusion barrier and the second diffusion barrier may include different materials from each other.

Abstract: A flash memory device includes a plurality of flash memory cell arrays, wherein: a flash memory cell array in the plurality of flash memory cell arrays comprises a plurality of layers of flash memory cell planes; and a flash memory cell plane includes a plurality of flash memory cells. The flash memory device further includes a logic circuitry coupled to the plurality of flash memory cell arrays, configured to perform operations using the plurality of flash memory cell arrays; and a sensing circuitry configured to access a corresponding flash memory cell plane among the plurality of flash memory cell planes.

Abstract: A semiconductor packaging structure includes a substrate, a wiring layer, a mask layer, and a sealing layer. The substrate has an effective region and a dummy region surrounding the effective region. The wiring layer is disposed on the effective and dummy regions, and is formed with a predetermined pattern including spaced-apart protrusions to define at least one cavity partially exposing the dummy region. The mask layer covers the wiring layer, and is formed with a through hole to communicate in space with the cavity. The through hole is smaller in size than the cavity, and cooperates with the cavity to form an accommodating space. The sealing layer covers the mask layer, and includes an engaging element filling the accommodating space and adhering to the substrate.

Abstract: A method of forming a semiconductor device includes: forming a first conductive feature in a first dielectric layer disposed over a substrate; forming a metal cap layer over an upper surface of the first conductive feature distal from the substrate; selectively forming a dielectric cap layer over an upper surface of the first dielectric layer and laterally adjacent to the metal cap layer, wherein the metal cap layer is exposed by the dielectric cap layer; and forming an etch stop layer stack over the metal cap layer and the dielectric cap layer, wherein the etch stop layer stack comprises a plurality of etch stop layers.

Abstract: A semiconductor device includes a semiconductor substrate; a first insulating film and a second insulating film provided above the semiconductor substrate; a low-k film provided between the first insulating film and the second insulating film; an element formation region in which elements included in an electric circuit are formed in the semiconductor substrate; a scribe region provided around the element formation region; a cut portion provided on the outer periphery of the scribe region; and a groove formed between the cut portion and the element formation region, wherein the groove penetrates through the low-k film.

Abstract: Provided is a mask which includes a mask body having a plurality of through hole portions and including a polymer film and a plurality of magnetic particles dispersed in the polymer film, and a polymer coating layer disposed on an outer surface of the mask body. Accordingly, the time and cost of manufacturing a mask are reduced and the precision of a deposition process is improved as well, so that the manufacturing yield of a display panel using the mask is improved and a display panel manufactured using the same has improved reliability.

Abstract: In some embodiments, the present disclosure relates to an integrated chip (IC) including a conductive structure disposed within a dielectric structure along a first side of a semiconductor substrate, an insulating structure disposed along inner sidewalls of the semiconductor substrate, the inner sidewalls of the semiconductor substrate extending through the semiconductor substrate, a blocking layer disposed along inner sidewalls of the insulating structure, and a through-substrate via (TSV) comprising a first portion and a second portion, the first portion extending from a second side of the semiconductor substrate to a horizontally-extending surface of the insulating structure that protrudes outward from the inner sidewalls of the insulating structure, the second portion extending from the first portion to the conductive structure and has a maximum width less than that of the first portion.

Abstract: A display panel includes a substrate including a transmissive area, a first non-display area surrounding the transmissive area, and a display area at least partially surrounding the first non-display area; display elements in the display area and each including a pixel electrode; scan lines in the display area, at least one of which extending through the first non-display area and detouring along an edge of the transmissive area; a connection line in the first non-display area and at least partially overlapping at least one of the scan lines, and on a first layer that is a same layer as the pixel electrode; a first line on a second layer different from the first layer; and a second line on a third layer different from the first layer and at an opposite side with respect to the first line.

Abstract: A method for making a micro LED display panel not requiring high-accuracy or individual positioning includes providing a carrier substrate with micro LEDs, providing a TFT substrate including a driving circuit, and forming a conductive connecting element, an insulating layer, and a contact electrode layer on the TFT substrate. The insulating layer and the contact electrode layer are patterned to define a through hole, the first electrode is placed against the contact electrode layer, and different voltages Vref and Vdd are applied to the contact electrode layer and to the conductive connecting element respectively, creating an electrostatic attraction. The micro LEDs and the first electrode are transferred from the carrier substrate onto the TFT substrate; and the conductive connecting element is bonded to the first electrode. The method of making is simple. A micro LED display panel made by the method is also provided.

Abstract: An apparatus and method is provided for coating a surface of a material with a film of porous coordination polymer. A first substrate having a first surface to be coated is positioned in a processing chamber such that the first surface is placed in a substantially opposing relationship to a second surface. In some embodiments, the second surface is provided by a wall of the processing chamber, and in other embodiments the second surface is provided by a second substrate to be coated. The first substrate is held such that a gap exists between the first and second surfaces, and the gap is filled with at least one reaction mixture comprising reagents sufficient to form the crystalline film on at least the first surface. A thin gap (e.g., having a thickness less than 2 mm) between the first and second surfaces is effective for producing a high quality film having a thickness less than 100 ?m.