Abstract: Generally, examples described herein relate to deposition masks and methods of manufacturing and using such deposition masks. An example includes a method for forming a deposition mask. A mask layer is deposited on a substrate. Mask openings are patterned through the mask layer. A central portion of the substrate is removed to define a substrate opening through a periphery portion of the substrate. The mask layer with the mask openings through the mask layer extending across the substrate opening.

Abstract: Disclosed are support substrates, methods of fabricating semiconductor packages using the same, and methods of fabricating electronic devices using the same. The support substrate comprises a main body, and a plurality of first protrusions finely protruding from an upper surface of the main body. The main body and the first protrusions include the same material and are formed as a unitary structure. The first protrusions are spaced apart from each other in first and second directions intersecting each other, when viewed in plan.

Abstract: A method of fabrication in a vacuum chamber. The method comprises: deploying the wafer within the vacuum chamber; applying a mask in a first position over the wafer in the vacuum chamber; following this, performing a first fabrication step comprising projecting material onto the wafer through the mask while in vacuum in the vacuum chamber; then operating a mask-handling mechanism deployed within the vacuum chamber in order to reposition the mask to a second position while remaining in vacuum in the vacuum chamber, wherein the repositioning comprises receiving readings from one or more sensors sensing a current position of the mask and based thereon aligning the current position of the mask to the second position; and following this repositioning, performing a second fabrication step comprising projecting material onto the wafer through patterned openings in the repositioned mask while still maintaining the vacuum in the vacuum chamber.

Abstract: A mask assembly, an apparatus for manufacturing a display device, and a method of manufacturing a display device are provided. A mask assembly includes: a mask frame including a frame body portion and dividers, the frame body portion being arranged at an outside of the mask frame, and the dividers dividing an inside of the frame body portion into a plurality of openings, each of the dividers being connected in a first direction and a second direction; and a plurality of mask sheets arranged on a top surface of the mask frame, coupled to the mask frame, and including at least one pattern opening, mask sheets of the plurality of mask sheets being apart from each other in the first direction.

Abstract: First and second wells are formed in a semiconductor substrate. First and second trenches in the first second wells, respectively, each extend vertically and include a central conductor insulated by a first insulating layer. A second insulating layer is formed on a top surface of the semiconductor substrate. The second insulating layer is selectively thinned over the second trench. A polysilicon layer is deposited on the second insulating layer and then lithographically patterned to form: a first polysilicon portion over the first well that is electrically connected to the central conductor of the first trench to form a first capacitor plate, a second capacitor plate formed by the first well; and a second polysilicon portion over the second well forming a floating gate electrode of a floating gate transistor of a memory cell having an access transistor whose control gate is formed by the central conductor of the second trench.

Abstract: An embodiment relates to a semiconductor component, comprising a semiconductor body of a first conductivity type comprising a voltage blocking layer and islands of a second conductivity type on a contact surface and optionally a metal layer on the voltage blocking layer, and a first conductivity type layer comprising the first conductivity type not in contact with a gate dielectric layer or a source layer that is interspersed between the islands of the second conductivity type.

Abstract: Described are plasma immersion ion implantation methods that use multiple precursor gases, particularly for the purpose of controlling an amount of a specific atomic dopant species that becomes implanted into a workpiece relative to other atomic species that also become implanted into the workpiece during the implantation process.

Abstract: According to various aspects, exemplary embodiments are disclosed of thermal interface materials, electronic devices, and methods for establishing thermal joints between heat spreaders or lids and heat sources. In exemplary embodiments, a method of establishing a thermal joint for conducting heat between a heat spreader and a heat source of an electronic device generally includes positioning a thermal interface material (TIM1) between the heat spreader and the heat source.

Abstract: According to one embodiment, a semiconductor manufacturing device according to an embodiment of the present invention includes a chamber; and a stage, wherein the stage comprises: a holding member arranged in the chamber, the holding member having a plurality of convex parts on a surface for mounting a substrate; and a plurality of pins moving up and down in a vertical direction with respect to the holding member, the plurality of lift pins rotating around a rotating shaft parallel to the vertical direction, wherein the plurality of lift pins rotates the substrate around the rotating shaft.

Abstract: A chip package assembly and a method for manufacturing the same are provided. A die is attached to one of pins located around a chip carrier, so that an electronic component such as a diode is packaged in the chip package assembly and is electrically connected in series with other dies inside the package, thereby improving the degree of integration of the chip package assembly, and reducing a volume of the external circuit.

Abstract: A MgO layer is formed using a process flow wherein a Mg layer is deposited at a temperature <200° C. on a substrate, and then an anneal between 200° C. and 900° C., and preferably from 200° C. and 400° C., is performed so that a Mg vapor pressure >10?6 Torr is reached and a substantial portion of the Mg layer sublimes and leaves a Mg monolayer. After an oxidation between ?223° C. and 900° C., a MgO monolayer is produced where the Mg:O ratio is exactly 1:1 thereby avoiding underoxidized or overoxidized states associated with film defects. The process flow may be repeated one or more times to yield a desired thickness and resistance×area value when the MgO is a tunnel barrier or Hk enhancing layer. Moreover, a doping element (M) may be added during Mg deposition to modify the conductivity and band structure in the resulting MgMO layer.

Abstract: The present disclosure relates to a method and device for decreasing generation of surface oxide of aluminum nitride. In a physical vapor deposition process, the aluminum nitride is deposited on a substrate in a deposition chamber to form an aluminum nitride coated substrate. A cooling chamber and a cooling load lock module respectively perform a first stage cooling and a second stage cooling on the aluminum nitride coated substrate in vacuum environments, so as to prevent the aluminum nitride coated substrate with the high temperature from being exposed in an atmosphere environment to generate the surface oxide. The method and device for decreasing the generation of the surface oxide of the aluminum nitride can further eliminate crystal defects caused by that gallium nitride is deposited on the surface oxide of the aluminum nitride in the next process.

Abstract: A nitride semiconductor laminate includes: a substrate comprising a group III nitride semiconductor and including a surface and a reverse surface, the surface being formed from a nitrogen-polar surface, the reverse surface being formed from a group III element-polar surface and being provided on the reverse side from the surface; a protective layer provided at least on the reverse surface side of the substrate and having higher heat resistance than the reverse surface of the substrate; and a semiconductor layer provided on the surface side of the substrate and comprising a group III nitride semiconductor. The concentration of O in the semiconductor layer is lower than 1×1017 at/cm3.

Abstract: A laminate including a glass plate and a coating layer, wherein the coating layer includes one or more components selected from the group consisting of silicon nitride, titanium oxide, alumina, niobium oxide, zirconia, indium tin oxide, silicon oxide, magnesium fluoride, and calcium fluoride, wherein a ratio (dc/dg) of a thickness dc of the coating layer to a thickness dg of the glass plate is in a range of 0.05×10?3 to 1.2×10?3, and wherein a radius of curvature r1 of the laminate with negating of self-weight deflection is 10 m to 150 m.

Abstract: In one embodiment, a semiconductor device includes a first insulator, a plurality of interconnections provided in the first insulator. The device further includes a second insulator provided on the first insulator and the plurality of interconnections, and a conductor provided on a first interconnection among the plurality of interconnections and having a shape that is projected upwardly with respect to the first interconnection in the second insulator. The device further includes a plug provided on the first interconnection via the conductor. The device further includes a first pad provided above the plug and electrically connected to the plug, and a second pad provided on the first pad and electrically connected to the first pad.

Abstract: A device includes a substrate having a first-face and a second-face. An electrode is provided in a through hole that penetrates through the substrate between the first-face and the second-face. A first-insulator is provided in the substrate and protrudes in a radial direction from an opening end of the through hole on a side close to the second-face to a center of the through hole as viewed from above the first-face. A second-insulator protrudes in the radial direction from the first-insulator as viewed from above the first-face, is thinner than the first-insulator, and is in contact with the electrode. A third-insulator is provided between an inner wall of the through hole and the electrode, and includes a first-portion that is in contact with the first-insulator and a second-portion that is in contact with the inner wall of the through hole and is closer to the second-face than the first-portion.

Abstract: The present disclosure provides a semiconductor device structure with a manganese-containing interconnect structure and a method for forming the semiconductor device structure. The semiconductor device structure includes a first interconnect structure disposed in a semiconductor substrate, a dielectric layer disposed over the semiconductor substrate, and a second interconnect structure disposed in the dielectric layer and electrically connected to the first interconnect structure. The first interconnect structure includes a first conductive line, and a first manganese-containing layer disposed over the first conductive line. The second interconnect structure includes a second conductive line, and a second manganese-containing layer disposed between the second conductive line and the dielectric layer.

Abstract: Disclosed is a coating made of an organic material on a mold for glass molding. The coating comprises CrxWyN(1-x-y), where 0.15<x<0.4, and 0.2?y?0.45. The coating has excellent high temperature resistance and anti-adhesion properties, thus being a promising coating material for molds.

Abstract: A transparent display device including a base substrate, a plurality of pixels disposed on the base substrate, each pixel having an emission area and a transmission area transparent to external light, a circuit element layer disposed on the base substrate, a first electrode disposed on the circuit element layer and corresponding to the emission area, a pixel define layer disposed on the circuit element layer, the pixel define layer including a first sidewall defining the emission area and a second sidewall defining the transmission area, an emission layer disposed on the first electrode and corresponding to the emission area, and a second electrode disposed on the emission layer and including an opening that corresponds to the transmission area, in which the first sidewall is inclined at a first angle, and the second sidewall is inclined at a second angle greater than the first angle.

Abstract: The present disclosure describes a method for the fabrication of ruthenium conductive structures over cobalt conductive structures. In some embodiments, the method includes forming a first opening in a dielectric layer to expose a first cobalt contact and filling the first opening with ruthenium metal to form a ruthenium contact on the first cobalt contact. The method also includes forming a second opening in the dielectric layer to expose a second cobalt contact and a gate structure and filling the second opening with tungsten to form a tungsten contact on the second cobalt contact and the gate structure. Further, the method includes forming a copper conductive structure on the ruthenium contact and the tungsten contact, where the copper from the copper conductive structure is in contact with the ruthenium metal from the ruthenium contact.