Abstract: A delay line of individually selectable delay elements can operate as an oscillator in an open loop mode to track process variation or drive a clock signal that varies with temperatures and voltages in the system. The delay line oscillator can also operate in a closed loop mode to match a frequency given by a tuner ratio and a reference clock. The delay line can also be used for measuring clock jitter or duty cycle.

Abstract: Signal modulation apparatus for applying a modulation signal to a carrier signal, the apparatus comprising: an amplitude modulator for modulating the amplitude of the carrier signal in accordance with a control signal; first mixing means for mixing together fractions of the carrier signal before and after action of the amplitude modulator to produce a first detection signal indicative of the amplitude modulation applied by the amplitude modulator; and detection means for comparing the control signal with a first detection signal to evaluate distortion in the first detection signal as compared with the control signal.

Abstract: Spread spectrum clock generators and electronic devices including the same are provided. A spread spectrum clock generator may include an oscillation circuit that is configured to receive a first spread spectrum clock signal and to output an average frequency signal corresponding to an average frequency of the first spread spectrum clock signal. The spread spectrum clock generator may also include a phase lock loop that is configured to receive the average frequency signal and to generate a second spread spectrum clock signal. The spread spectrum clock generator may further include a control circuit that is configured to receive the first and second spread spectrum clock signals and to output a phase lock loop control signal to control the phase lock loop such that an average frequency of the second spread spectrum clock signal approaches the average frequency of the first spread spectrum clock signal.

Abstract: An analog-to-digital converter (ADC) suitable for measuring on-die DC or low frequency analog voltages may include a ring oscillator having a group of circuit cells successively and circularly coupled. Under certain circumstances, the ring oscillator may produce an output frequency that corresponds substantially linear to the input voltage. Other embodiments may be disclosed or claimed.

Abstract: A voltage controlled oscillator (VCO) securing a wide range of variable amount of oscillatory frequency is provided. In the VCO, a resistor R1 and a capacitor C1 are connected in series on a line of a crystal resonator and a control voltage supply terminal, a cathode of a variable-capacitance diode VD1 is connected between the R1 and the C1, and an anode of the VD1 is grounded. A parallel-connected circuit is disposed between the C1 and a port connected with the crystal resonator, the parallel-connected circuit including a variable-capacitance diode VD2 and a capacitor C3 connected in series, an expansion coil L1, and a Q dump resistor R6 which are connected in parallel. The parallel-connected circuit on an input side is grounded via a resistor R4, and a point between the R1 and the C1 and a point between the VD2 and the C3 are connected via a resistor R5.

Abstract: The semiconductor integrated circuit includes a first oscillator, a second oscillator (PLL), a third oscillator (ring oscillator), a selector that switches, in turn, based on a clock of the third oscillator, and outputs a clock of the first oscillator or a clock of the second oscillator, and a determination circuit that counts up or counts down the clock output from the selector, based on the clock of the third oscillator, determines the correspondence of the clock output from the selector and the clock of the third oscillator, based on a result of the counting up or the counting down, and determines whether either of the clock output from the selector or the clock of the third oscillator occur an abnormal oscillation.

Abstract: Disclosed is a semiconductor integrated circuit device that includes a ring oscillator circuit, performs a proper oscillation operation, and expands the range of oscillation frequency variation. The ring oscillator circuit includes, for instance, plural differential amplifier circuits. MOS transistors are respectively added to input nodes of a differential pair of the differential amplifier circuits. Further, gate control circuits are incorporated to control the gates of the MOS transistors, respectively. The gate control circuits cause the MOS transistors to function as an amplitude limiter circuit in mode 3, exercise control to turn off the amplitude limiter circuit in mode 2, and use the amplitude limiter circuit to start oscillation in mode 1.

Abstract: An oscillator having a plurality of operatively coupled ring oscillators arranged in hyper-matrix architecture. The operatively coupled ring oscillators are either identical or non-identical and are coupled through a common inverter or tail current transistors.

Abstract: Systems and methods for operating with oscillators configured to produce an oscillating signal having an arbitrary frequency are described. The frequency of the oscillating signal may be shifted to remove its arbitrary nature by application of multiple tuning signals or values to the oscillator. Alternatively, the arbitrary frequency may be accommodated by adjusting operation one or more components of a circuit receiving the oscillating signal.

Abstract: A terahertz oscillator may include a first insulating layer, an electron emitter on the first insulating layer, adapted to emit an electron beam, and including a cathode, an anode, an oscillating circuit, and a collector sequentially disposed, spaced apart from each other, on the first insulating layer in a direction in which the electron beam is emitted from the electron emitter, wherein the oscillating circuit converts energy of the electron beam to energy of an electromagnetic wave, and wherein the collector collects the electron beam, an output unit adapted to emit the electromagnetic wave from the oscillating circuit to outside of the terahertz oscillator, and an electron emitting material layer. The cathode may include a first curved portion that extends in a direction perpendicular to the first insulating layer. The electron emitting material layer may be on an inner surface of the first curved portion of the cathode.

Abstract: The phase-frequency detector (PFD) includes a frequency detector (FD) arranged to receive orthogonal signal pairs of a reference signal and a feedback signal and estimate a frequency error between a reference signal and a feedback signal; a FD voltage-to-current converter arranged to convert the frequency error into a first current; a phase detector (PD) arranged to receive the orthogonal signal pairs and estimate a phase error between the reference signal and the feedback signal, and a PD voltage-to-current converter arranged to convert the phase error into a second current.

Abstract: The phase locked loop has a phase-frequency detector (PFD), a loop filter (LF), a voltage controlled oscillator (VCO), and a 3-stage frequency divider. The PFD receives a reference signal and a feedback signal to determine phase and frequency errors. The LF), coupled to the phase-frequency detector, filters the phase and frequency errors to generate a control voltage. The VCO, coupled to the loop filter, generates a VCO output signal according to the control voltage. The 3-stage frequency divider, coupled to the voltage controlled oscillator, divides the frequency of the VCO output signal 3 times to generate the feedback signal. The 3-stage frequency divider comprises three cascaded frequency dividers with different rangers of operating frequencies.

Abstract: According to one embodiment, a local oscillator includes a digitally-controlled oscillator that outputs an oscillating signal having a frequency N times as large as an oscillating frequency according to an oscillator tuning word; a frequency divider that performs a 1/N frequency division of the oscillating signal, and outputs a 2N phase clock; a counter that counts the clock and outputs the count value as integer oscillator phase data based upon a reference signal; a first flip-flop that latches the clock with the reference signal, and outputs the resultant as first phase information; a variable delay circuit that delays the reference signal and outputs the resultant as a delay reference signal; a second flip-flop that latches the clock with the delay reference signal, and outputs the resultant as second phase information; a delay control unit that controls a delay amount of the variable delay circuit; a data conversion unit that outputs fractional oscillator phase data based upon the first and second phase i

Abstract: An oscillation signal with a selectable frequency is generated with a phase locked loop (10, 12, 14). The oscillator (10) of the loop receives a feedback signal, to which an offset is added in order to reduce transient effects when a frequency modification is made. A first and second offset control value are used to control the offset successively. The first offset control value is controlled by a combination of the frequency settings before and after the modification. The second offset control value is controlled by the frequency settings after the modification. The first and second offset control values are used to control an offset of applying to a frequency control signal of an oscillator (10) of the phase locked loop (10, 12, 14). The offset controlled by the first control offset value is applied during a predetermined time interval before the offset controlled by the second control offset value is applied.

Abstract: A semiconductor integrated circuit includes a ring oscillator and a noise canceller. The ring oscillator includes first and second signal generators. The first signal generator is configured to generate a first output signal having a first phase based on an input signal. The second signal generator is configured to generate a second output signal having a second phase different from the first phase based on the input signal. The noise canceller includes first and second amplifiers and an arithmetic module. The first amplifier is configured to amplify the first output signal generated by the first signal generator using a first amplification factor. The second amplifier is configured to amplify the second output signal generated by the second signal generator using a second amplification factor. The arithmetic module is configured to combine the first output signal amplified by the first amplifier with the second output signal amplified by the second amplifier.

Abstract: An apparatus and method for digital up converting in a mobile communication system are provided. The apparatus includes a Selectable Input Logic (SIL), a Scalable Clock Distribution Logic (SCDL), a filter logic, and a mixer logic. The SIL performs decimation at a decimation rate. The SCDL controls a clock frequency. The filter logic performs channel filtering for the decimated signal, and performs interpolation at an interpolation rate variable. The mixer logic up-converts the signal provided from the filter logic.

Abstract: Adjustable circuit components may be formed from arrays of differential circuit elements such as differential capacitors and differential current sources. The differential circuit elements may each have a control input. The differential circuit elements in each array of differential circuit elements may be connected in parallel between first and second terminals. A thermometer code control signal may be provided to the control inputs to adjust the capacitance, current, or other parameter associated with the adjustable circuit component. Adjustable circuit components may also be formed from an array of capacitors or other circuit elements having successively increasing strengths.

Abstract: Disclosed herein is a delay circuit for a low power ring oscillator. The delay circuit includes: a pair of N type transistors that receive first differential input signals Vin1+ and Vin1?; a pair of P type transistors that receive second differential input signals Vin2+ and Vin2?; a differential output terminal that outputs differential output signals Vout+ and Vout? generated from the pair of N type transistors and the pair of P type transistors; an N type detector that supplies a body voltage to the pair of N type transistors; and a P type detector that supplies a body voltage to the pair of P type transistors.

Abstract: A demodulator for demodulating a modulated signal has a peak detector (206) with an input (100) coupled to receive the modulated signal and an output (207) to supply a peak detector output signal. The peak detector has a charge storer (314) coupled to the peak detector output so that the peak detector output signal is provided by a voltage across the charge storer (314) and a comparator (313) having a first comparator input coupled to the peak detector input to receive the modulated signal and a second comparator input coupled to the peak detector output to receive the peak detector output signal. The comparator (313) provides a comparison signal representing a comparison between the voltage of the modulated signal and the peak detector output signal.

Abstract: A resonator has a vibrating element (10) and at least a first (20) and a second (30) electrode, at least one of the electrodes storing an electric charge to make the device charge biased. A charge adjuster (C) can add to or reduce the stored charge. The charge adjuster can be a capacitor to reduce leakage, and or a power supply coupled by switch. It can reduce problems of stiction, and reduce power consumption, and reduce non linearity's, it enables the charge level to be adjusted before operation. A second switch can be used to ground the vibrating element.