Abstract: In a CDR (clock data recovery) deserializer, a clock divider receives a recovered clock signal (SCLK) and generates a divided clock signal (RPCLK). The frequency of the divided clock signal is lowered with each cycle of the divided clock signal being generated for each count of cycles of the recovered clock signal up to a predetermined ratio number. A serial-to-parallel shift register shifts in recovered serial data bits with each cycle of the recovered clock signal and outputs the predetermined ratio number of the shifted recovered serial data bits at a predetermined transition of every cycle of the divided clock signal. A SYNC (synchronization) detect logic asserts a VRS (diVider ReSet) signal coupled to the clock divider for controlling the clock divider to generate the predetermined transition for a cycle of the divided clock signal when the VRS signal is asserted.

Abstract: In a digital filter of a DPLL (digital phase locked loop) for minimizing the bit error rate for multiple communications protocols, a first reloadable register portion stores a TBW (total bandwidth) value programmed into the first reloadable register portion through a first port, and a second reloadable register portion stores a DBW (differential bandwidth) value programmed into the second reloadable register portion through a second port. An up—counter generates an UP—CNT value by counting up each UP signal pulse generated by a phase transition detector when a first phase of a SDIN (serial data input) signal leads a second phase of a current ACLK (recovered clock) signal. A down—counter generates a DOWN—CNT value by counting up each DOWN signal pulse generated by the phase transition detector when the first phase of the SDIN (serial data input) signal lags the second phase of the current ACLK (recovered clock) signal.

Abstract: Schema conversion approaches convert images of complex objects. The schema conversion is performed on images of complex objects belonging to a root class, whether those objects are instances of the root class or instances of a subclass of the root class. A complex object is an object that is comprised of a collection of objects or that has another object as an attribute. The approaches use change vectors to represent changes to make to an image to convert it between the target schema version and source schema version. Change vectors are generated based on schema version records, each of which describes the properties of a schema version, including the attributes in the schema version and the data type of each of the attributes. The approaches evolve changes that includes addition, modification and deletion of object attributes. They convert from an earlier schema version to a later schema version, and vice versa, i.e. from a later schema version to a earlier schema version.

Abstract: A database managing apparatus, which can immediately obtain desired data from a database. A database managing apparatus includes a CPU, an input/output device, a main memory and an external memory. The CPU has a controller that initially obtains one article record from stored records via the input/output device. The controller reads out definition data in a database definition file. Then, the controller classifies the obtained records according to attributions based on the definition data. The controller does not compress the data regarding the record group belonging to the attribution A, which is the record group to be searched, but compresses data regarding the record groups belonging to the attributions B-E, which are the record groups other than the record group to be searched. As a result, the controller can reduce the unnecessary decompression of record data belonging to other attributions than the attribution to be searched. As a result, the controller can quickly retrieve the requested record.

Abstract: A system provides referencing from one file system server to another through the use of a file system location database, improving movement and replication of file systems. When a file system is moved from a first file system server, a data object that references the file system remains in the first server and contains information used to find the current location of the file system. The actual location of the file system is stored in the separate file system location database, which contains the locations of file systems on a number of file system servers. This allows the data in a file system to be replicated or moved without requiring updates to the data in any redirecting or referencing servers.

Abstract: A device and method for filtering added information, in which PSI (Program Specification Information) in a transport stream is processed in an MPEG-2 system layer, are provided. The device includes a memory for storing table IDs and version numbers of sections for each of the table IDs, a combination of at least one of the sections forming a table which added information defines; a comparing unit for determining matching of a table ID included in the present section and the table IDs stored in the memory upon reception of the section, and comparing the version number of the matched table ID to the version number of a received section number; and a section processing unit for receiving and processing the present section if it is determined that the version number stored in the table ID is not the same as the version number of the received section, where by reducing a size and complexity of hardware, i.e.

Abstract: A garbage collection system and method in a multiprocessor environment having a shared memory wherein two or more processing units participate in the reclamation of garbage memory objects. The shared memory is divided into regions or heaps and all heaps are dedicated to one of the participating processing units. The processing units generally perform garbage collection operations, i.e., a thread on the heap or heaps that are dedicated to that the processing unit. However, the processing units are also allowed to access and modify other memory objects, in other heaps when those objects are referenced by and therefore may be traced back to memory objects within the processing units dedicated heap. The processors are synchronized at rendezvous points to prevent reclamation of used memory objects.

Abstract: Process aimed at the extraction of electrical signals emanating from the two ends of a two wire link between two installations exchanging data, wherein a probe comprising an attenuation cell is plugged in on either side of a break point situated on the line pair, then the connections thus established are isolated in such a way as to transfer the signals to the attenuation cell, the attenuation cell is activated by progressive withdrawal of active components, high-impedance signals are tapped off at the two ends of the attenuation cell, and signals which are images of the electrical signals dispatched by one or other of the ends of the line pair are obtained as output from the attenuation cell, after analogue calculation based on subtraction of the signals and multiplication by a constant which is directly related to the value of the attenuation of the cell.

Abstract: A method for tracking a locally generated spread spectrum signal sequence includes the step of correcting the spread spectrum signal sequences with respect to the synchronization time in an early/late interval. The correlation responses are subtracted from one another and the clock of the locally generated spread spectrum signal sequence is controlled as a function of the subtraction. Correlations are performed through the use of at least two hierarchically staggered closed-loop controls having different early/late intervals. The early interval of the one closed-loop control having a small early/late interval must not become earlier than the early interval of the other closed-loop control system having a next-larger early/late interval. Furthermore, the late intervals of the one closed-loop control system having a small early/late interval must not become later than the late interval of the other closed-loop control system having a next-larger early/late interval.

Abstract: A method and apparatus estimate an offset between a carrier frequency of a transmitter and a local reference frequency of a receiver. A received signal is separated into frequency synchronization signals and data, and a determination is made whether the frequency synchronization signals are adequate for estimating the frequency offset. This determination may be made based on, e.g., an estimated Doppler spread, an estimated signal to noise ratio, and/or an available amount of frequency offset estimation time. The frequency offset is estimated based on the determination results. If the frequency synchronization signals are adequate for estimating the frequency offset, the frequency synchronization signals are used for determining the frequency offset. Otherwise, the rate of the frequency synchronization signals is increased, e.g., by using the data as frequency synchronization signals, in which case the data is combined with the frequency synchronization signals to determine the frequency offset.

Abstract: A servo channel digitally processes the data read from a magnetic media. The channel uses both edges of a system clock to detect peaks and generates position error systems by an area-based automatic gear control loop. By altering the sample delay, the channel digitally, up-samples at higher rates without requiring a higher system clock.

Abstract: A circuit (10) for producing a single output data (DOUT) stream and a corresponding single clock signal (CLKOUT). This circuit comprises an input for receiving a single input data stream (DIN), where the input data stream has data words at a first frequency. This circuit further includes a plurality of clock inputs for receiving a plurality of corresponding clock signals (CLK0, CLK1), where each of the plurality of corresponding clock signals is synchronized to a corresponding plurality of the data words. This circuit still further includes an input for receiving a fast clock signal (CLKF), where the fast clock signal has a fast frequency greater than the first frequency. The circuit also includes various circuitry. This circuitry includes circuitry for sampling (L20, L21) the input data stream at the fast frequency, circuitry for outputting (M, LM) the sampled data as the single output data stream, and circuitry for outputting (CG) the single clock cycle in response to the fast clock signal.

Abstract: The invention provides apparatus and methods for generating the coefficients of a finite impulse response digital filter used in signal sample rate conversion. Sequence generation circuitry provides a discrete-time sequence x(n) that is coupled to a plurality of cascaded discrete-time integrators that generate the filter coefficients h(n). Bit serial and interleaved bit serial implementations are described that provide efficient coefficient generators. The described apparatus and methods also may be used to efficiently implement a finite impulse response digital filter for an oversampling analog-to-digital converter.

Abstract: A power calculator calculates the power of an input signal in accordance with a component of an input received signal. A comparator asserts an unmodulated signal detection signal when the power calculated by the power calculator exceeds a prescribed threshold. A maximum value detector detects the maximum power of the input received signal in accordance with the assertion of the unmodulated signal detection signal and generates non-modulated signal position instruction information with a maximum value detection signal, and a frequency error calculator calculates an error of a carrier frequency on the basis of the received signal corresponding to the maximum power. The frequency error is calculated only with a non-modulated signal, whereby the frequency error can be correctly calculated and the non-modulated signal position can also be correctly detected.

Abstract: A method and spread spectrum transceiver for demodulating a spread spectrum signal is disclosed. A spread spectrum phase shift keyed (PSK) modulated information signal is received within a demodulator of a spread spectrum receiver on a signal channel. The information signal includes a sequence of data symbols formed from a plurality of high rate mode chips. A precursor portion of the signal channel is Viterbi detected. A multi-state trellis is formed having a predetermined number of states. A post-cursor portion of the signal channel is feedback equalized with a finite impulse response filter having feedback taps operatively connected to a chip detection circuit that tracks high rate mode chips and a carrier loop circuit for phase and frequency tracking. The information signal is despread within a spread spectrum code function correlator.

Abstract: A receiver for detecting spread spectrum binary data particularly on a power line in the presence of channel distortion. In one embodiment a standard pattern ideally suited for minimal distortion in the channel is used in conjunction with an alternate pattern which is developed to better detect carrier and data in the presence of certain channel distortion. The receiver switches between the standard and alternate pattern to provide improved detection. In another embodiment an adaptive pattern is used which is developed from the receive signal. For instance, the signal over several bit times is averaged to provide a pattern which is correlated with a receive signal.

Abstract: A method of design and an implementation system for reduced-state Viterbi detectors for intersymbol interference channels are provided. The method uses a complement states grouping technique that comprises the steps of finding the state distances between complement states; forming the reduced-state trellis by grouping the complement states with state distance no less than the minimum free distance; and by keeping the complement states with state distance less than minimum free distance unchanged. The resultant reduced-state Viterbi detector has negligible performance loss compared to the full-state Viterbi detector while the complexity is reduced by a factor of about two.

Abstract: A trellis decoder identifies the closest points from each coset in a four dimensional trellis decoder by reading a received point and determining upper and lower threshold values in a signal constellation to define a decode region within the constellation. The dimensions of the decode region are based on the number of bits of information in the received signal. The decoder translates the received point in four directions to provide four image points. Any imaged point that transitions outside the constellation decode region is mapped into the decode region to ensure that the four image points are within the decode region of the constellation. For each of the cosets, bit extraction is then performed to find the closest point to the received point. Once the closest coset points are identified, the trellis decoder performs a maximum likelihood sequence estimation using the Viterbi algorithm to determine the received sequence.

Abstract: Systems for periodically determining and digitally representing the phase and/or frequency of an input signal are disclosed which include a frequency discriminator, a phase discriminator and a control network. The frequency and phase discriminators may be used to periodically sample and estimate, respectively, the frequency and phase of an input analog signal, and these estimates are provided to a control network which calculates an error estimate and adjusts the estimate of the frequency provided by the frequency discriminator based on this estimate of the error. The systems of the present invention may further include means for digitally representing the phase and/or frequency of the input signal, and may also include a frequency-to-phase converter coupled to the output of the control network which converts the adjusted output of the frequency discriminator into a phase value. Associated methods for extracting and digitizing phase and frequency information from an analog input signal are also disclosed.

Abstract: A pulse code modulation modem system is configured to transmit data from a first modem to a second modem over the public switched telephone network (PSTN). The PSTN employs robbed bit signaling (RBS) such that symbols affected by RBS arrive at the second modem in a periodic manner based on a period of six symbols. The modem system is configured such that signal segments are formatted and transmitted with six symbols per segment. After obtaining symbol synchronization, the second modem initializes a modulo-6 symbol counter such that the zero count corresponds to the first symbol of each received signal segment. Those symbols affected by RBS are identified and analyzed to determine optimized signal point constellations that may be used to compensate for the RBS on a symbol-by-symbol basis during subsequent encoding and decoding. Upon a loss of synchronization, the second modem resets its modulo-6 counter in response to the detection of the first symbol in a subsequent signal segment.