Abstract: A data receiver equalization technique utilizes a receiver clock that has a frequency different that the incoming data frequency (i.e., an “asynchronous clock”) to asynchronously sample the incoming data waveform. The resulting information about the data, typically including the rise and/or fall times, overshoot and/or undershoot, and amplitude, may be used to equalize a data channel. Other adjustments to the receiver, including the gain level and DC offset compensation, may also be made using the resulting information. An illustrative embodiment using clocked comparators, continuous-time comparators, and a statistical analysis circuit is shown.

Abstract: An apparatus and method for compensating audio signals to be recorded on an optical disc to optimize usage of memory in an audio decoding circuit, and to neutralize invalid audio data to produce good audio quality. A determination is made with regard to whether audio data signals contain normal data or invalid data. Invalid data is adjusted into normal audio data, and stored in the memory. The volume of the data stored in the memory is monitored to detect overflow and underflow conditions of the memory, a data transmitting stopping signal being sent during an overflow condition of the memory, a data transmitting requesting signal being sent during an underflow condition. The audio data reproduced from the memory is decoded, and the decoded audio data is output. Undesired errors are prevented by monitoring the reproduced audio data for invalid data and by adjusting invalid data into normal data when detected.

Abstract: A transmission device has labeling means adapted to map each symbol of a first alphabet to secondary digital data belonging to a second alphabet having Q symbols, Q being strictly greater than P, wherein P symbols of the second alphabet each exclusively represent one and only one symbol of the first alphabet. A coder determines redundant data belonging to the second alphabet, using coding rules that take into account the secondary digital data. A transmitter modulates a physical quantity into a series of signals each capable of taking a number P of different values, and according to transmission rules successively representing the digital data to be transmitted and the redundant data.

Abstract: Briefly, in accordance with one embodiment of the invention, a method of performing high speed signaling includes the following. A preamble signal and an end of packet (EOP) signal are transmitted at a low frequency using rail-to-rail voltage signal levels. Later, high frequency signaling is transmitted using a voltage signal level swing that is less than rail-to-rail.

Abstract: A spread spectrum communications system that is operable to provide user-selectable data transfer rates comprises a user station for generating an access request and a gateway server for receiving the access request. The gateway server includes a rate unit for comparing a requested rate to assigned rates, a selector for selecting an available user channel and an available signaling alphabet, and an allocation unit for assigning the carrier, user channel, and alphabet to the access request. One of several offered transfer rates is assigned to the available user channel. Each offered rate corresponds to a set of signaling alphabets with low cross-correlation for data transfer.

Abstract: A digital audio broadcasting receiver includes: an analog-digital converter for converting a plurality of transfer frames from an analog signal format into a digital signal format based on a clock signal having a fixed frequency and for outputting the first transfer frame; a demodulator for demodulating the first transfer frame from a first frame processing start position for the first transfer frame; an audio decoder for generating audio data containing a plurality of audio samples based on the data symbol contained in the first transfer frame which has been demodulated by the demodulator; a transfer path characteristics calculator for generating a transfer path characteristics signal representing transfer path characteristics based on the reference symbol contained in the first transfer frame which has been demodulated by the demodulator; and a frame processing start position control section for controlling a second frame processing start position for the second transfer frame, by outputting to the demodula

Abstract: A clock synchronizing circuit enables initial synchronization of clock in spite of the case of modulation system except for quadrature modulation with simple constitution. A cosine/sine output circuit inputs thereto an integration clock ‘ICLK’, a sampling signal ‘SSAMP’, a sign switching signal ‘SPM’, a cosine component integration signal ‘SCCI’, and a sine component integration signal, before obtaining a cosine signal ‘SCOS’ corresponding to a cosine component of initial phase of a symbol clock and a sine signal ‘SSIN’ corresponding to a sine component thereof. An angular detector inputs thereto the cosine signal ‘SCOS’ and the sine signal ‘SSIN’, before obtaining initial phase of the symbol clock ‘SCLK’.

Abstract: A DSL communication system including a DSL transmission unit at a central office (DTU-C) and a DSL transmission unit at a remote location (DTU-R) in communication over a communication link. DTU-C and DTU-R synchronize or train at a first data rate. After synchronization, DTU-C and/or DTU-R measure the line quality at the first data rate. The line quality may be measured based on bit-error-rate, attenuation level and/or signal-to-noise ratio. A second data rate is then selected based on the line quality measurements. DTU-C may then initiate a rate change request, according to which DTU-C and DTU-R may re-synchronize at the second rate. The second rate may be several data rates higher or lower than the first data rate.

Abstract: A bidirectional direct sequence spread spectrum half-duplex RF modem which can be applied to transmit and receive numerous types of analog and digital pulse modulation. The modem incorporates two different SAW devices fabricated on a single monolithic substrate. A first SAW device is used as a resonator in the oscillator circuit while a second SAW device is used as the correlator for transmit and receive operations. The RF modem operates as an analog or digital pulse transmitter and receiver and is adapted to be generic and versatile enough to be used in many different types of data communication systems, such as OOK, PWM and PPM. The RF modem can be used as the physical (PHY) layer in a layered communication system such as the ISO OSI communication stack. In an alternative embodiment, the transmission bit rate is increased using a plurality of correlators wherein each is configured with a unique function (i.e., code) that is orthogonal with all other functions.

Abstract: A baud rate detector detects baud rate of received serial data based on an AT command included in the serial data. A character discriminator detects parity type and data format of the serial data based on the AT command in the serial data. An information relay 16 sets the baud rate, the parity type and the data format to a register in a UART (Universal Asynchronous Receiver-Transmitter). A clock generator generates a clock signal for data reception and supplies the clock signal to the UART.

Abstract: Modern fiber optic networks typically transfer data using encoding in which the clock is transmitted along with the data, for example in NRZ format. In order to use the clock to process the data, the clock signal must be extracted from the data signal. Because the data and clock may travel through different circuit paths they may have different propagation delays and a phase offset between the clock and data may result. Data and clock phase offsets are more problematical as data transmission speed increases. Furthermore the data/phase offset is typically not constant and may change with a variety of variables. To compensate for the changing offset, one or more variable delays are inserted in the phase detector circuitry. The timing of the variable delay is controlled by a bang-bang phase detector, such as an Alexander phase detector, which determines if the clock is leading, lagging, or in phase with the data.

Abstract: Updated opening code and parameters can be reprogrammed into a modem system with no disassembly of the modem hardware. The modem system includes a memory chip in which operating code and parameters are stored. Two control programs control the reprogramming of updated operating code. One of the control programs is designed for manufacturing and testing purposes. The other control program allows remote reprogramming of updated operating code or parameters from a remote location such as a customer site. A user can thus remotely upgrade system firmware with updates, bug fixes, enhancements or other new releases of system operating code by downloading the update over a phone line to a host PC and reprogramming the memory chip of the modem over the serial port from the host PC. The user can also remotely upgrade the modem system firmware by directly programing the memory chip of the modem without the assistance of the host PC. The modem system is portable, obtaining power from a standard 9 volt battery.

Abstract: A synchronous circuit controller includes a delay section for delaying data with a predetermined amount of delay, and outputting corresponding delay data, a latch section for latching each of the data in synchronization with a clock, and outputting latch data, a comparator circuit for comparing the latch data to each other in the ascending order of the amount of delay, detecting matching or non-matching between signals to be compared, and outputting comparison signals corresponding to the detection results, respectively, and a selector circuit for selecting one of the data as synchronous data in response to control of the comparison signal.

Abstract: A computer system couples multiple function units using channels having full-duplex, low power, point-to-point interconnect. Each function unit couples to the channel via a Channel Interface Block (CIB). The CIB includes a transmitter and a receiver. The receiver includes an integrating sampling capacitor, pass-gates having particular resistive characteristics, an auto-zero inverter, and a set of inverter stages for squaring the output of the inverter. These components are used to implement sampled-data methods and structures that perform received data extraction from the full-duplex channel signal.

Abstract: A mobile wireless transceiver selects one of multiple nearby base stations to facilitate communication over a wireless network. Each base station transmits a pilot signal that includes a spreading signal transmitted at one of many possible phase offsets. The wireless transceiver selects an initial one of the possible phase offsets of the spreading signal and then correlates a received signal against the spreading signal at consecutive ones of the possible phase offsets. Correlation begins at the selected initial phase offset and continues until a component of the received signal and the spreading signal are aligned, indicating the detection of the pilot signal from one of the base stations.

Abstract: A system (20) for communicating request information from a first circuit (state machine A) operable according to a first clock domain (CLKA) to a second circuit (state machine B) operable according to a second clock domain (CLKB). In the system, the first clock domain differs from the second clock domain. The system comprises a flag circuit (F2) for storing a flag having a changeable state. The flag circuit comprises an input for receiving a toggle control signal (TOGGLE) and the state of the flag changes in response to assertion of the toggle control signal, where the first circuit is operable to assert the toggle signal to communicate the request information to the second circuit. The system further comprises a synchronizing circuit (SCD) having an input coupled to an output of the flag circuit and for receiving the state of the flag. The system further comprises a detection circuit (ED) having an input coupled to an output of the synchronizing circuit.

Abstract: A clock reproducing circuit for reproducing a clock signal accurately from a PSK modulated signal so as to sample the I's aperture point. The phase of the PSK modulated signal is rotated by a phase rotation circuit (1) by a predetermined angle according to the transition angle between adjoining reception points, and the phase difference due to the time difference between the zero cross point position at which the adjoining reception points of the phase-rotated PSK modulated signal intersect the I-axis or the Q-axis and the time center position of the adjoining reception points is detected by a phase difference detecting circuit (2). According to the phase difference detected, the oscillation frequency of a voltage-controlled oscillator (5) is controlled to accurately reproduce the clock to be sampled at the I aperture.

Abstract: A digital broadcasting receiver in which one decoder decodes both Reed-Solomon codes for TMCC and Reed-Solomon codes of an MPEG2-TS packet of a main signal. The received data is divided into a main signal and a TMCC signal. When the separated main signal is subjected to deinterleaving by a deinterleaving circuit (503), the burst symbol signal is eliminated, and the TMCC signal separated subsequent to the main signal in the last frame of a superframe is added by a selector (509). The received data to which the TMCC signal is added is decoded by a basic Reed-Solomon code decoder (510) so as to carry out the error correction of the main signal and the TMCC signal.

Abstract: A process and interface for interconnection of multiprocessor modules by point-to-point serial-to-parallel links. Data processing or data communication modules (A and B) are interconnected by means of high-speed point-to-point serial links conveying multiplexed information organized into frames comprising a start-of-frame recognition pattern. The process, on transmission and on reception, performs an analog synchronization of the basic clocks of the modules to a reference clock generated by one of the modules designated as a reference module, called the master module, the other modules being called slave modules, and a digital synchronization of the start-of-frame of each slave module to the start-of-frame sent by the master module.

Abstract: A training process for a filter such as included in a time domain equalizer for an xDSL transceiver includes a novel spectral estimation process for a channel. The spectral estimation determines the taps of the filter using an overdetermined set of equations based on the auto-correlation estimates of the received signal. A weighting function such as a sigmoidal function is applied to the AC coefficients to change the relative weighting of the AC coefficients. Upon solving for the taps of the filter using a fitting criterion such as the least square error criterion, the filter significantly reduces the impulse response of the channel.

Abstract: Process for inhibiting crust formation in reactors used for polymerising alpha-olefines, such as ethylene and propylene, in the presence of particles of catalytic solids containing titanium and chlorine in the combined state.The polymerisation is carried out in the presence of an amount of a silicone oil which is less than 1% by weight, relative to the weight of catalytic solid.