Abstract: A system for publishing data on shared broadcast channels using spread-spectrum techniques, which may comprise a spread-spectrum encoder capable of receiving data and placing it in a spread-spectrum signal format and a transmitter operating on a shared communication channel or frequency band, such as might be allocated to terrestrial point-to-point or broadcast communications. The shared communication channel may comprise a cellular system, in which data may be transmitted using spread-spectrum techniques using the transmitters and repeaters of the cellular system simultaneously with voice and other transmissions associated with the cellular system. A subscriber station may be capable of receiving using a plurality of different communication channels or frequency bands, such as a first receiver capable of cellular reception and a second receiver capable of satellite reception, at least one of which uses spread-spectrum techniques.

Abstract: A digital desynchronizer (10) includes an elastic store unit (12) that receives a synchronously mapped asynchronous data signal (14) and outputs asynchronous output data over an asynchronous output data signal (20) in response to an output clock signal (22). The output clock signal (22) is generated by a digitally controlled oscillator (24). The digitally controlled oscillator (24) receives a speed up signal (28) and a slow down signal (30) from a jitter accumulator (26) in order to adjust the clock rate of the output clock signal (22). The jitter accumulator (26) compares retimed read address information (32) to write address information (34) from the elastic store unit (12), subtracts an initial bias, adds the result to any previous sum, and compares this final result to programmable threshold levels in order to determine whether or not to assert the speed up signal (28) or the slow down signal (30).

Abstract: A intelligent power management apparatus for use with a matched-filter. A multiplexer multiplexes shifted-in-phase chips and shifted-quadrature-phase chips from an in-phase-shift register and a quadrature-phase-shift register, respectively, to generate multiplexed chips. The multiplexed chips include alternating sets of shifted-in-phase chips and shifted-quadrature-phase chips. A controller generates a POWERDOWN signal when the multiplexed chips from a received-spread-spectrum signal are unlikely to have a particular-chip sequence. The controller generates an ACTIVATION signal when the multiplexed chips are likely to have the particular-chip sequence present. An adder tree generates a CORRELATION signal when the multiplexed chips have the particular-chip sequence and match or correlate with the settings of the adder tree.

Abstract: A technique for modulating and demodulating CPM spread spectrum signals and variations of CPM spread spectrum signals. A transmitter divides a signal data stream into a plurality of data streams (such as I and Q data streams), independently modulates the I and Q data streams using CPM or a related technique, and superposes the plurality of resultants for transmission. A receiver receives the superposed spread spectrum signal and simultaneously attempts to correlate for a plurality of chip sequences (such as I and Q chip sequences), and interleaves the correlated I and Q data streams into a unified signal data stream. In one embodiment, the receiver separates the received spread spectrum signal into real and imaginary parts, attempts to correlate both real and imaginary parts for a plurality of chip sequences, and combines the real I, real Q, imaginary I, and imaginary Q signals into a unified signal data stream.

Abstract: A spread spectrum radiocommunication device includes a plurality of digital data demodulators which are independently operated to track the paths of a multipath radio signal transmitted from a to-be-communicated device and PN code generators each of which has a ROM storing PN codes and which are respectively provided in the digital data demodulators. In a control section, a ROM address latched by an address latch circuit is monitored and a PN address relative value is generated, and the PN address relative value is added to a basic address generated from an address counter in an address adder and the added address is supplied to the PN code ROM to generate a PN code.

Abstract: A generalized form of a multimodulus algorithm (GMMA) is described for use in blind equalization. A receiver uses a signal point constellation representing 256 levels. This signal space is divided into sample, or data, subsets. Cost function minimization is done with respect to each sample subset.

Abstract: A digital information bit that has been encoded and transmitted as a first modulated signal from a first transmitter in the presence of a second modulated signal that has been transmitted by a second transmitter is received and decoded by receiving a composite signal that is a sum of the first modulated signal and the second modulated signal. The composite signal is processed to generate a complex numerical sample. Then, a plurality of bit pairs are hypothesized, wherein each hypothesized bit pair includes a hypothesized first information bit encoded and transmitted by the first transmitter and a hypothesized second information bit encoded and transmitted by the second transmitter. For each of the plurality of hypothesized bit pairs, a path metric is generated that is indicative of a likelihood that information sequence estimates are accurate estimates, wherein the information sequence estimates include the hypothesized first and second information bits.

Abstract: For use in an automatic gain control that receives a digital signal from a digital circuit having a given dynamic range and develops therefrom a gain signal to be applied to a variable gain amplifier, an analyzing circuit for, and method of, determining a magnitude of the gain signal.

Abstract: A Viterbi decoding circuit for decoding an input signal is provided. The circuit contains a detector, a first converter, a Viterbi decoder, a second converter, and a selector. The input signal is grouped into a current and subsequent input signal group. The detector detects negative peak data values and positive peak data values from the current input signal group. The first converter converts the positive and negative peak data in a reverse direction to produce reverse positive and negative peak data, respectively. The Viterbi-decoder decodes the reverse positive and negative peak data with respect to a predetermined number of initial states and generates current reverse decoded data groups which respectively correspond to a plurality of channels and respectively correspond to the initial states. In addition, the Viterbi decoder generates a control signal based on a state of initial decoded data corresponding to the subsequent input signal group.

Abstract: A spread spectrum communication apparatus includes at least one surface acoustic wave matched filter, a plurality of surface acoustic wave delay lines having different delay amounts, and integrating circuits for integrating an output signal of the surface acoustic wave matched filter and the respective output signals of the plurality of surface acoustic wave delay lines.

Abstract: A method and a system for providing synchronization in a stream of messages. In such a method and system, the stream of messages is arranged in fictitious sequences of messages, in which messages of a predetermined type may only occupy a certain number of locations within a sequence. In this way, the messages of the predetermined type are concentrated in a part of the sequence, which allows a receiver to use the time during which the remaining part of the sequence is transmitted for other purposes, such as scanning of the reception band, etc.

Abstract: An UWB receiver utilizing a microwave tunnel diode as a single pulse detector for short pulse, impulse, baseband or ultra wideband signals. The tunnel diode detector's bias point is set at system start-up, through an automatic calibration procedure to its highest sensitivity point relative to the desired bit error rate performance (based upon internal noise only) and remains there during the entire reception process. High noise immunity is achieved through the use of a high speed, adaptive dynamic range extension process using a high speed, Gallium Arsenide (GaAs) voltage variable attenuator (VVA) whose instantaneous attenuation level is determined by a periodic sampling of the ambient noise environment. Microprocessor-controlled detector time-gating is performed to switch the tunnel diode detector to the receiver front end circuitry for reception of an incoming UWB pulse, and alternately to ground through a resistor to discharge stored charge on the tunnel diode detector.

Abstract: A method of, and apparatus for, symbol timing recovery, comprising asynchronously sampling a signal burst at a predetermined plurality of times per symbol period, combining corresponding samples occurring in successive sampling cycle periods, making a soft decision on each combination of samples, and selecting for demodulation a timing offset(i) giving the largest soft decision.

Abstract: A cordless direct sequence spread spectrum telephone using a direct conversion radio architecture wherein the code sequence used for spreading and despreading is an even code sequence to prevent addition of low frequency noise in the down-conversion process, the preferred even code being a 12-chip code and, more particularly, being an even 12-chip code that is generated by adding one bit to an inverted, shifted, and/or reversed 11-chip Barker sequence.

Abstract: A logical block is disclosed for decoding a data sequence encoded by a convolutional code, in which a given number of states are to be evaluated. These given states are assigned the given number of state memories which store an associated path and an accumulated distance value. The given number of state memories are associated with parallel processing blocks which each have, as the smallest group to be processed in parallel, two state memories to be read from first and second parallel processing blocks, and two state memories to be written into third and fourth parallel processing blocks. Optimum memory organization permits simple parallel processing and reduction in circuit complexity.

Abstract: A received signal has been converted from a source symbol rate to another symbol rate by symbol repetition, then interleaved to form frames in which the same symbol sequence is repeated multiple times. The source symbol rate is identified by dividing each frame into various numbers of blocks, and determining whether each such division makes at least a certain proportion of the blocks identical. The source symbols are reproduced by identifying a subset of similar blocks from statistical properties of the blocks, and combining the signal values in the subset of blocks.

Abstract: A frequency-hopping-communications system, assigned a system bandwidth B, with the system bandwidth B divided into N sets of frequencies, with each set of the N sets of frequencies not having the same frequencies as other sets of the N sets of frequencies, for communicating base-message data to a plurality of remote units. The frequency-hopping-communications system includes a plurality of base stations for communicating base-message data to the plurality of remote units. Each of the base stations has a coverage area divided into a plurality of concentric regions with each concentric region assigned one of the N sets of frequencies.

Abstract: A technique for modulating and demodulating CPM spread spectrum signals and variations of CPM spread spectrum signals. A transmitter divides a signal data stream into a plurality of data streams (such as I and Q data streams), independently modulates the I and Q data streams using CPM or a related technique, and superposes the plurality of resultants for transmission. A receiver receives the superposed spread spectrum signal and simultaneously attempts to correlate for a plurality of chip sequences (such as I and Q chip sequences), and interleaves the correlated I and Q data streams into a unified signal data stream. In one embodiment, the receiver separates the received spread spectrum signal into real and imaginary parts, attempts to correlate both real and imaginary parts for a plurality of chip sequences, and combines the real I, real Q, imaginary I, and imaginary Q signals into a unified signal data stream.

Abstract: A noise detection and delay receiver circuit includes a circuit input and output and a plurality of individual receiver circuits connected to the input having trip points which range from a low trip point to a high trip point. Edge detect circuitry and delay circuitry are used to prevent the output from changing back to the previous state for a period of time immediately after it has just changed state. Multiple transitions of the input voltage across the trip points of the individual receivers are used to delay the response until noise has settled out of the input signal.

Abstract: A communication system (10) includes a rotationally invariant pragmatic trellis coded modulation (PTCM) encoder (18) and decoder (34). The PTCM encoder (18) partitions information bits (20) into primary (42) and secondary (44) data streams. A pilot bit (56) is inserted into the secondary data stream (44) during each frame (46). The secondary stream (44) then receives rate 1/2 convolutional encoding (60) that is punctured to a rate of 9/16. The primary data stream (42) is differentially encoded (50). The encoded primary and secondary streams are concurrently phase mapped (70) using an 8-PSK constellation so that an effective code rate of 5/6 results. The PTCM decoder (34) convolutionally decodes (84) the secondary stream, then re-encodes secondary stream estimates using a systematic, transparent convolutional encoder (88). The pilot bit is evaluated (92) in the re-encoded symbol estimates (90) to detect and correct any secondary stream inversion that may have occurred due to phase ambiguity.