Abstract: Provided is a semiconductor device which allows an alignment mark used for the manufacturing of a solid-state image sensor (semiconductor device) having a back-side-illumination structure to be formed in a smaller number of steps. The semiconductor device includes a semiconductor layer having a first main surface and a second main surface opposing the first main surface, a plurality of photodiodes which are formed in the semiconductor layer and in each of which photoelectric conversion is performed, a light receiving lens disposed over the second main surface of the semiconductor layer to supply light to each of the photodiodes, and a mark for alignment formed inside the semiconductor layer. The mark for alignment is formed so as to extend from the first main surface toward the second main surface and have a protruding portion protruding from the second main surface in a direction toward where the light receiving lens is disposed.

Abstract: A semiconductor device includes a device isolation region defining an active region in a substrate, and gate structures buried in the active region of the substrate. At least one of the gate structures includes a gate trench, a gate insulating layer conformally formed on an inner wall of the gate trench, a gate barrier pattern conformally formed on the gate insulating layer disposed on a lower portion of the gate trench, a gate electrode pattern formed on the gate barrier pattern and filling the lower portion of the gate trench, an electrode protection layer conformally formed on the gate insulating layer disposed on an upper portion of the gate trench to be in contact with the gate barrier pattern and the gate electrode pattern, a buffer oxide layer conformally formed on the electrode protection layer, and a gate capping insulating layer formed on the buffer oxide layer to fill the upper portion of the gate trench.

Abstract: According to an embodiment, a nonvolatile semiconductor memory device comprises: a semiconductor layer; a first gate insulating film; a plurality of floating gate electrodes; a second gate insulating film; a plurality of control gate electrodes; and an upper insulating film. The semiconductor layer is provided on a substrate and extends in a first direction. The floating gate electrode is formed on the semiconductor layer via the first gate insulating film. The control gate electrode faces the upper surface of the floating gate electrode via the second gate insulating film. Moreover, the control gate electrode extends in a second direction intersecting the first direction. The upper insulating film is formed on an upper portion of the plurality of control gate electrodes. Moreover, a height of an upper surface of the upper insulating film changes along the second direction.

Abstract: Semiconductor structures are fabricated to include strained epitaxial layers exceeding a predicted critical thickness thereof.

Abstract: A method for forming spacers of a transistor gate having an active layer surmounted by the gate, including forming a porous layer covering the gate and having a dielectric constant equal to or less than that of silicon oxide, forming a protective layer covering the porous layer and the gate, etching the protective layer anisotropically to preserve residual portions of the protective gate only at the flanks of the gate, forming a modified layer by penetration of ions within the porous layer anisotropically to modify the porous layer over its entire thickness above the gate and above the active layer and so as not to modify the entire thickness of the porous layer on the flanks of the gate, the latter being protected by protective spacers constituting porous spacers, and removing the modified layer by etching to leave the protective spacers in place.

Abstract: A semiconductor device includes a substrate having a first and second region, a first structure and a second structure. The first structure is formed over the substrate in the first region. The first structure has a first height. The second structure is formed over the substrate in the second region. The second structure has a second height different from the first height.

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a semiconductor device includes: a substrate; a first region over the substrate, the first region comprising a first n type material; a second region over the substrate and laterally adjacent to the first region, the second region comprising a first p type material; a third region disposed within the second region and laterally separated from the first region, the third region comprising a second n type material; a fourth region disposed atop the third region, the fourth region comprising a second p type material; a fifth region disposed within the first region and laterally separated from the second region, the fifth region comprising a third p type material; and a sixth region disposed atop the fifth region, the sixth region comprising a third n type material.

Abstract: According to one embodiment, a method of manufacturing a semiconductor device comprises forming through holes extending through a semiconductor substrate in a thickness direction to integrated circuits in chip areas, and forming a first mark opening and second mark openings in a dicing line. The method detects the first mark opening based on positions of the second mark openings. Then, the method performs alignment of exposure positions based on the position of the first mark opening to perform photolithography, thereby forming a resist pattern on the back side of the semiconductor substrate.

Abstract: A semiconductor device configured to provide high heat dissipation and improve breakdown voltage comprises a substrate, a buried oxide layer over the substrate, a buried n+ region in the substrate below the buried oxide layer, and an epitaxial layer over the buried oxide layer. The epitaxial layer comprises a p-well, an n-well, and a drift region between the p-well and the n-well. The semiconductor device also comprises a source contact, a first electrode electrically connecting the source contact to the p-well, and a gate over a portion of the p-well and a portion of the drift region. The semiconductor device further comprises a drain contact, and a second electrode extending from the drain contact through the n-well and through the buried oxide layer to the buried n+ region. The second electrode electrically connects the drain contact to the n-well and to the buried n+ region.

Abstract: Provided is an optical semiconductor device includes: a light-emitting layer having a first main surface, a second main surface opposed to the first main surface, a first electrode and a second electrode which are formed on the second main surface; a fluorescent layer provided on the first main surface; a light-transmissive layer provided on the fluorescent layer and made of a light-transmissive inorganic material; a first metal post provided on the first electrode; a second metal post provided on the second electrode; a sealing layer provided on the second main surface so as to seal in the first and second metal posts with one ends of the respective first and second metal posts exposed; a first metal layer provided on the exposed end of the first metal post; and a second metal layer provided on the exposed end of the second metal post.

Abstract: An image sensor includes: a first inter-layer dielectric layer formed over a front side of a substrate including photoelectric conversion regions; isolation structures each of which penetrates through the first inter-layer dielectric layer and has a portion buried in the substrate; first metal lines formed over the first inter-layer dielectric layer to correspond to the photoelectric conversion regions; and an optical filter and a light condenser formed over a back side of the substrate.

Abstract: An EMI shielding package structure includes a substrate unit having a first surface with a die mounting area and a second surfaces opposite to the first surface, metallic pillars formed on the first surface, a chip mounted on and electrically connected to the die-mounting area, an encapsulant covering the chip and the first surface while exposing a portion of each of the metallic pillars from the encapsulant, and a shielding film enclosing the encapsulant and electrically connecting to the metallic pillars. A fabrication method of the above structure by two cutting processes is further provided. The first cutting process forms grooves by cutting the encapsulant. After a shielding film is formed in the grooves and electrically connected to the metallic pillars, the complete package structure is formed by the second cutting process, thereby simplifying the fabrication process while overcoming inferior grounding of the shielding film as encountered in prior techniques.

Abstract: Disclosed are a semiconductor device, a light emitting device, and a method of manufacturing the same. The semiconductor device includes a substrate, a plurality of rods aligned on the substrate, a metal layer disposed on the substrate between the rods, and a semiconductor layer disposed on and between the rods. Electrical and optical characteristics of the semiconductor device are improved due to the metal layer.

Abstract: The present disclosure relates to a semiconductor device substrate and a method for making the same. The semiconductor device substrate includes a first dielectric layer, a second dielectric layer and an electronic component. The first dielectric layer includes a body portion, and a wall portion protruded from a first surface of the body portion. The wall portion has an end. The second dielectric layer has a first surface and an opposing second surface. The first surface of the second dielectric layer is adjacent to the first surface of the body portion. The second dielectric layer surrounds the wall portion. The end of the wall portion extends beyond the second surface of the second dielectric layer. The electronic component includes a first electrical contact and a second electrical contact. At least a part of the electronic component is surrounded by the wall portion.

Abstract: A semiconductor device is improved in reliability. A power MOSFET for switching, and a sense MOSFET for sensing a current flowing in the power MOSFET, which is smaller in area than the power MOSFET, are formed in one semiconductor chip. The semiconductor chip is mounted over a chip mounting portion, and sealed in a resin. To first and second source pads for outputting the current flowing in the power MOSFET, a metal plate is bonded. A third source pad for sensing the source voltage of the power MOSFET is at a position not overlapping the metal plate. A coupled portion between a source wire forming the third pad and another source wire forming the first and second pads is at a position overlapping the metal plate.

Abstract: A semiconductor structure with a MISFET and a HEMT region includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A third III-V compound layer is disposed on the second III-V compound layer is different from the second III-V compound layer in composition. A source feature and a drain feature are disposed in each of the MISFET and HEMT regions on the third III-V compound layer. A gate electrode is disposed over the second III-V compound layer between the source feature and the drain feature. A gate dielectric layer is disposed under the gate electrode in the MISFET region but above the top surface of the third III-V compound layer.

Abstract: A finFET structure, and method of forming such structure, in which a germanium enriched nanowire is located in the channel region of the FET, while simultaneously having silicon-germanium fin in the source/drain region of the finFET.

Abstract: A light emitting device according to the embodiment includes a first conductive semiconductor layer; an active layer on the first conductive semiconductor layer; a second conductive semiconductor layer on the active layer; a first passivation layer surrounding the first conductive semiconductor layer, the active layer, and the second conductive semiconductor layer; a second connection layer electrically connected to the second conductive semiconductor layer through the first passivation layer; a first light extracting structure layer on the first passivation layer and the second connection layer; a first electrode layer electrically connected to the first conductive semiconductor layer; and a second electrode layer on the first light extracting structure layer.

Abstract: A method includes placing a device having a titanium nitride layer into a chamber. The device also has a mask that includes a photoresist material and an aluminum copper hardmask. The method also includes performing an ashing process on the mask using the chamber. The method further includes, after the ashing process, performing an etching process using the chamber to etch through portions of the titanium nitride layer. Performing the etching process includes flowing a gas mixture containing tetrafluoromethane (CF4) and oxygen gas (O2) into the chamber at a temperature of at least about 200° C.

Abstract: Various apparatuses and methods are disclosed. An interconnect may include molding material configured to support a light-emitting device, and an electrical trace arranged with the molding material to electrically couple the light-emitting device to a power source, wherein the electrical trace has an electrical insulator on at least a portion thereof. A light-emitting apparatus may include a light-emitting device, molding material supporting the light-emitting device, and an electrical trace arranged with the molding material to electrically couple the light-emitting device to a power source, wherein the electrical trace has an electrical insulator on at least a portion thereof.