Patents Examined by Jesse Y Miyoshi
  • Room temperature tunneling switches and methods of making and using the same
    Patent number: 9825154
    Abstract: The tunneling channel of a field effect transistor comprising a plurality of tunneling elements contacting a channel substrate. Applying a source-drain voltage of greater than a turn-on voltage produces a source-drain current of greater than about 10 pA. Applying a source-drain voltage of less than a turn-on voltage produces a source-drain current of less than about 10 pA. The turn-on voltage at room temperature is between about 0.1V and about 40V.
    Type: Grant
    Filed: November 28, 2012
    Date of Patent: November 21, 2017
    Assignee: Michigan Technological University
    Inventor: Yoke Khin Yap
  • Extra gate device for nanosheet
    Patent number: 9818650
    Abstract: A method for forming semiconductor devices includes forming a highly doped region. A stack of alternating layers is formed on the substrate. The stack is patterned to form nanosheet structures. A dummy gate structure is formed over and between the nanosheet structures. An interlevel dielectric layer is formed. The dummy gate structures are removed. SG regions are blocked, and top sheets are removed from the nanosheet structures along the dummy gate trench. A bottommost sheet is released and forms a channel for a field effect transistor device by etching away the highly doped region under the nanosheet structure and layers in contact with the bottommost sheet. A gate structure is formed in and over the dummy gate trench wherein the bottommost sheet forms a device channel for the EG device.
    Type: Grant
    Filed: August 23, 2016
    Date of Patent: November 14, 2017
    Assignee: International Business Machines Corporation
    Inventors: Bruce B. Doris, Terence B. Hook, Junli Wang
  • Thermal sensor including pulse-width modulation output
    Patent number: 9816871
    Abstract: Some embodiments include apparatuses and methods having a node to receive ground potential, a first diode including an anode coupled to the node, a second diode including an anode coupled to the node, a first circuit to apply a voltage to a cathode of each of the first and second diodes to cause the first and second diodes to be in a forward-bias condition, and a second circuit to generate a signal having a duty cycle based on a first voltage across the first diode and a second voltage across the second diode. At least one of such the embodiments includes a temperature calculator to calculate a value of temperature based at least in part on the duty cycle of the signal.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: November 14, 2017
    Assignee: Intel IP Corporation
    Inventor: Matthias Eberlein
  • Metal shield structure and methods for BSI image sensors
    Patent number: 9812492
    Abstract: A backside illumination image sensor structure comprises an image sensor formed adjacent to a first side of a semiconductor substrate, wherein an interconnect layer is formed over the first side of the semiconductor substrate, a backside illumination film formed over a second side of the semiconductor substrate, a metal shielding layer formed over the backside illumination film and a via embedded in the backside illumination film and coupled between the metal shielding layer and the semiconductor substrate.
    Type: Grant
    Filed: April 13, 2015
    Date of Patent: November 7, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shiu-Ko JangJian, Chi-Cherng Jeng, Volume Chien, Ying-Lang Wang
  • Honeycomb cell structure three-dimensional non-volatile memory device
    Patent number: 9812461
    Abstract: A monolithic three-dimensional memory device includes a plurality of memory stack structures arranged in a hexagonal lattice and located over a substrate. The hexagonal lattice structure is defined by hexagons each having a pair of sides that are parallel to a first horizontal direction and perpendicular to a second horizontal direction, the memory stack structures are located at vertices of the hexagonal lattice, and each memory stack structure includes vertically spaced memory elements and a vertical semiconductor channel. Source contact via structures are located at each center of a subset of the hexagons that forms a one-dimensional array that extends along the second horizontal direction, each source contact via structure being electrically shorted to a respective source region over, or within, the substrate.
    Type: Grant
    Filed: March 17, 2015
    Date of Patent: November 7, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yasushi Doda, Ryoichi Honma
  • Semiconductor structure and fabricating method thereof
    Patent number: 9812577
    Abstract: A semiconductor structure and a method of fabricating the semiconductor structure are provided. The semiconductor structure includes a substrate; a metal gate structure on the substrate; and a spacer next to the metal gate structure having a skirting part extending into the metal gate structure and contacting the substrate. The metal gate structure includes a high-k dielectric layer and a metal gate electrode on the high-k dielectric layer.
    Type: Grant
    Filed: September 5, 2014
    Date of Patent: November 7, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Che-Cheng Chang, Tung-Wen Cheng, Chang-Yin Chen, Mu-Tsang Lin
  • Semiconductor devices
    Patent number: 9806204
    Abstract: A method of manufacturing a semiconductor device, the method including forming a tunnel insulating layer on an upper surface of a substrate, forming gate patterns on an upper surface of the tunnel insulating layer, forming capping layer patterns on sidewalls of the gate patterns and on the upper surface of the tunnel insulating layer, etching a portion of the tunnel insulating layer that is not covered with the gate patterns or the capping layer patterns to form a tunnel insulating layer pattern, and forming a first insulating layer on the upper surface of the substrate to cover the gate patterns, the capping layer patterns, and the tunnel insulating layer pattern, wherein the first insulating layer has an air gap between the capping layer patterns.
    Type: Grant
    Filed: November 7, 2014
    Date of Patent: October 31, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung-Soo Ahn, O Ik Kwon, Bum-Soo Kim, Hyun-Sung Kim, Kyoung-Sub Shin, Min-Kyung Yun, Seung-Pil Chung, Won-Bong Jung
  • Semiconductor device and manufacturing method thereof
    Patent number: 9805954
    Abstract: A manufacturing method forms an oxide insulating layer and a first plasma etching treatment forms a depressed portion therein. A second plasma etching treatment forms a trench including curved lower corner portions. An oxide semiconductor film is formed in contact with a bottom portion, the curved lower corner portions, and side portions of the trench. Source and electrodes are formed to be electrically connected to the oxide semiconductor film. A gate insulating layer is formed over the oxide semiconductor film and a gate electrode is formed over the gate insulating layer. The first plasma etching treatment is performed with a first bias power and a first power of a first power source, and the second plasma etching treatment is performed with a second bias power and a second power of a second power source, wherein the second bias power is lower than the first bias power.
    Type: Grant
    Filed: December 11, 2014
    Date of Patent: October 31, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Akihiro Ishizuka, Shinya Sasagawa
  • Method of forming source/drain contact
    Patent number: 9799567
    Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming a gate structure over a substrate. The gate structure includes a first hard mask layer. The method also includes forming a source/drain (S/D) feature in the substrate adjacent to the gate structure, forming a sidewall spacer along sidewalls of the gate structure. The sidewall spacer has an outer edge at its upper portion facing away from the gate structure. The method also includes forming a second spacer along sidewalls of the gate structure and along the outer edge of the sidewall spacer, forming dielectric layers over the gate structure, forming a trench extending through the dielectric layers to expose the source/drain feature while the gate structure is protected by the first hard mask layer and the sidewall spacer with the second spacer. The method also includes forming a contact feature in the trench.
    Type: Grant
    Filed: October 23, 2014
    Date of Patent: October 24, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Jhih Kuo, Yu-Hsien Lin, Hung-Chang Hsieh, Jhun Hua Chen
  • Low resistance contact for semiconductor devices
    Patent number: 9799747
    Abstract: A semiconductor device includes a substrate and a p-doped layer including a doped III-V material on the substrate. An n-type material is formed on or in the p-doped layer. The n-type layer includes ZnO. An aluminum contact is formed in direct contact with the ZnO of the n-type material to form an electronic device.
    Type: Grant
    Filed: March 12, 2015
    Date of Patent: October 24, 2017
    Assignee: International Business Machines Corporation
    Inventors: Joel P. de Souza, Keith E. Fogel, Jeehwan Kim, Devendra K. Sadana, Brent A. Wacaser
  • Methods of fabricating semiconductor devices
    Patent number: 9793165
    Abstract: A method of fabricating a semiconductor device is provided. The method may include preparing a substrate having a first surface and a second surface, forming a via hole exposing at least a portion of the substrate from the first surface of the substrate, forming a first insulating film on an inner wall of the via hole, forming a conductive connection part filling an inside of the via hole including the first insulating film, polishing the second surface of the substrate until the conductive connection part is exposed, and selectively forming a second insulating film on the second surface of the substrate using an electrografting method to expose the conductive connection part.
    Type: Grant
    Filed: January 6, 2012
    Date of Patent: October 17, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seyoung Jeong, Taeje Cho, Hogeon Song, Kyu-Ha Lee
  • Graphene-based solid state devices capable of emitting electromagnetic radiation and improvements thereof
    Patent number: 9793437
    Abstract: Described herein are solid-state devices based on graphene in a Field Effect Transistor (FET) structure that emits high frequency Electromagnetic (EM) radiation using one or more DC electric fields and periodic magnetic arrays or periodic nanostructures. A number of devices are described that are capable of generating and emitting electromagnetic radiation.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: October 17, 2017
    Assignee: p-brane LLC
    Inventor: Jay P. Morreale
  • Self-alignment for redistribution layer
    Patent number: 9786580
    Abstract: An apparatus comprising a substrate with multiple electronic devices. An interconnect structure formed on a first side of the substrate interconnects the electronic devices. Dummy TSVs each extend through the substrate and form an alignment mark on a second side of the substrate. Functional TSVs each extend through the substrate and electrically connect to the electronic devices. A redistribution layer (RDL) formed on the second side of the substrate interconnects ones of the dummy TSVs with ones of the functional TSVs. Step heights of the RDL over the functional TSVs are less than a predetermined value, whereas step heights of the RDL over the dummy TSVs are greater than the predetermined value.
    Type: Grant
    Filed: November 15, 2013
    Date of Patent: October 10, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ku-Feng Yang, Ming-Tsu Chung, Hong-Ye Shih, Jiung Wu, Chen-Yu Tsai, Hsin-Yu Chen, Tsang-Jiuh Wu, Wen-Chih Chiou
  • Supply self adjustment for systems and methods having a current interface
    Patent number: 9784779
    Abstract: A sensor system having a current interface includes a supply and current interface, an electronic control unit and an enhanced initialization sensor. The supply and current interface is configured to receive a supply voltage. The electronic control unit is coupled to the supply and current interface. The enhanced initialization sensor is coupled to the supply and current interface. The enhanced initialization sensor is configured to initialize the supply and current interface at a suitable current level to mitigate erroneous information.
    Type: Grant
    Filed: February 28, 2014
    Date of Patent: October 10, 2017
    Assignee: Infineon Technologies AG
    Inventors: Christoph Schroers, Christof Bodner, Simon Hainz
  • Method for base contact layout, such as for memory
    Patent number: 9786719
    Abstract: Embodiments disclosed herein may relate to forming a base contact layout in a memory device.
    Type: Grant
    Filed: March 7, 2012
    Date of Patent: October 10, 2017
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Antonino Rigano, Fabio Pellizzer, Gianfranco Capetti
  • Semiconductor arrangement and formation thereof
    Patent number: 9776858
    Abstract: A semiconductor arrangement and method of formation are provided. The semiconductor arrangement includes a MEMS device in a MEMS area, where a first metal layer is connected to a first metal connect adjacent the MEMS area and a cap is over the MEMS area to vacuum seal the MEMS area. A first wafer portion is over and bonded to the first metal layer which connects the first metal connect to a first I/O port using metal routing. The first metal layer and the first wafer portion bond requires 10% less bonding area than a bond not including the first metal layer. The semiconductor arrangement including the first metal layer has increased conductivity and requires less processing than an arrangement that requires a dopant implant to connect a first metal connect to a first I/O port and has a better vacuum seal due to a reduction in outgassing.
    Type: Grant
    Filed: February 26, 2014
    Date of Patent: October 3, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Hsin-Ting Huang, Hsiang-Fu Chen, Wen-Chuan Tai, Chia-Ming Hung, Shao-Chi Yu, Hung-Hua Lin, Yuan-Chih Hsieh
  • Semiconductor device and manufacturing method thereof
    Patent number: 9773878
    Abstract: A semiconductor device includes a first main electrode terminal and second main electrode terminal disposed on the principal surface of a semiconductor substrate so as to be spaced from one another, an insulating film formed on the principal surface of the semiconductor substrate, and a thin film resistance layer. One end side of the thin film resistance layer is connected to the first main electrode terminal and the other end side of the thin film resistance layer is connected to the second main electrode terminal, the thin film resistance layer being spirally formed on the insulating film in such a way as to surround the first main electrode terminal. The thin film resistance layer extends while oscillating in a thickness direction of the semiconductor substrate.
    Type: Grant
    Filed: July 7, 2015
    Date of Patent: September 26, 2017
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Takahide Tanaka, Masaharu Yamaji
  • Isolation structure of fin field effect transistor
    Patent number: 9773892
    Abstract: A representative fin field effect transistor (FinFET) includes a substrate having a major surface; a fin structure protruding from the major surface having a lower portion comprising a first semiconductor material having a first lattice constant; an upper portion comprising the first semiconductor material. A bottom portion of the upper portion comprises a dopant with a first peak concentration. A middle portion is disposed between the lower portion and upper portion, where the middle portion comprises a second semiconductor material having a second lattice constant different from the first lattice constant. An isolation structure surrounds the fin structure, where a portion of the isolation structure adjacent to the bottom portion of the upper portion comprises the dopant with a second peak concentration equal to or greater than the first peak concentration.
    Type: Grant
    Filed: February 5, 2016
    Date of Patent: September 26, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Ching, Guan-Lin Chen, Chao-Hsiung Wang, Chi-Wen Liu
  • Extra gate device for nanosheet
    Patent number: 9768079
    Abstract: A method for forming semiconductor devices includes forming a highly doped region. A stack of alternating layers is formed on the substrate. The stack is patterned to form nanosheet structures. A dummy gate structure is formed over and between the nanosheet structures. An interlevel dielectric layer is formed. The dummy gate structures are removed. SG regions are blocked, and top sheets are removed from the nanosheet structures along the dummy gate trench. A bottommost sheet is released and forms a channel for a field effect transistor device by etching away the highly doped region under the nanosheet structure and layers in contact with the bottommost sheet. A gate structure is formed in and over the dummy gate trench wherein the bottommost sheet forms a device channel for the EG device.
    Type: Grant
    Filed: September 14, 2016
    Date of Patent: September 19, 2017
    Assignee: International Business Machines Corporation
    Inventors: Bruce B. Doris, Terence B. Hook, Junli Wang
  • Enhancement of iso-via reliability
    Patent number: 9761482
    Abstract: A process of making a semiconductor structure. The process includes forming a wiring line; forming a reliability enhancement material on the wiring line; forming an interlayer dielectric (ILD) layer on the wiring line; forming a via opening through the ILD layer and reliability enhancement material to expose a surface of the wiring line; and filling the via opening with a metal to form a metal-filled via in contact with the wiring line wherein the reliability enhancement material is in direct contact with the metal-filled via; wherein the reliability enhancement material causes a compressive stress on the metal-filled via where it contacts the wiring line. Another embodiment includes the metal-filled via being an iso-via so that there is only one metal-filled via per wiring line.
    Type: Grant
    Filed: August 25, 2015
    Date of Patent: September 12, 2017
    Assignee: International Business Machines Corporation
    Inventors: Lawrence A. Clevenger, Baozhen Li, Xiao H. Liu, Kirk D. Peterson