Abstract: Multiple gate stack portions are formed in a gate cavity by direct metal gate patterning to provide FinFETs having different threshold voltages. The different threshold voltages are obtained by selectively incorporating metal layers with different work functions in different gate stack portions.
Type:
Grant
Filed:
January 23, 2017
Date of Patent:
February 27, 2018
Assignee:
GLOBALFOUNDRIES INC.
Inventors:
Ruqiang Bao, Siddarth A. Krishnan, Unoh Kwon, Keith Kwong Hon Wong
Abstract: A connection electrode for connecting a transistor including a semiconductor material other than an oxide semiconductor to a transistor including an oxide semiconductor material is smaller than an electrode of the transistor including a semiconductor material other than an oxide semiconductor that is connected to the connection electrode.
Type:
Grant
Filed:
July 29, 2014
Date of Patent:
February 27, 2018
Assignee:
Semiconductor Energy Laboratory Co., Ltd.
Abstract: A FinFET device structure is provided. The FinFET device structure includes a fin structure formed over a substrate and an isolation structure formed over the substrate. The FinFET device structure includes a first gate structure and a second gate structure formed over the fin structure. The first gate structure has a first top width in a direction that is parallel to the fin structure, the second gate structure has a second top width in a direction that is parallel to the fin structure, and the first top width is greater than the second top width.
Abstract: Inter-substrate coupling and alignment using liquid droplets can include electrical and plasmon modalities. For example, a set of droplets can be placed on a bottom substrate. A top substrate can be placed upon the droplets, which uses the droplets to align the substrates. Using the droplets in a capacitive or plasmon coupling modality, information or power can be transferred between the substrates using the droplets.
Type:
Grant
Filed:
October 29, 2014
Date of Patent:
February 13, 2018
Assignee:
Elwha LLC
Inventors:
William David Duncan, Roderick A. Hyde, Jordin T. Kare, Thomas M. McWilliams, Thomas Allan Weaver, Lowell L. Wood, Jr.
Abstract: An organic light emitting diode display device and a method for manufacturing the same are disclosed where permeation of moisture and oxygen may be prevented. The organic light emitting diode display device includes a protective members including an first inorganic film formed on a substrate to completely cover an organic light emitting diode, an organic film formed on the first inorganic film, and a second inorganic film formed on the first inorganic film and the organic film, wherein the organic film includes a first organic pattern corresponding to upper and side parts of the organic light emitting diode, and at least one second organic pattern being spaced from the first organic pattern and surrounding the first organic pattern, and the second organic pattern has an upper surface having the same height as an upper surface of the first organic pattern.
Type:
Grant
Filed:
December 30, 2014
Date of Patent:
February 6, 2018
Assignee:
LG Display Co., Ltd.
Inventors:
Yun-Ho Kook, Tae-Joon Song, Yong-Hee Han
Abstract: A light emitting element includes an anode, a light transmitting cathode, and a light emitting layer sandwiched therebetween, formed on a surface of a substrate. Light emitted by the light emitting layer by voltage being applied between the electrodes is output from a surface toward the side of the light transmitting electrode. A light scattering layer for scattering evanescent light generated at the surface is provided on the surface of the light transmitting electrode. The light scattering layer has a first scattering portion having an uneven structure and a lower refractive index than the light emitting layer, and second scattering portions that fill at least the bottoms of recesses of the uneven structure and has a different refractive index from the first scattering portion. The distance between the bottoms of the recesses and the surface of the light transmitting electrode is a seepage depth of the evanescent light or less.
Abstract: Inter-substrate coupling and alignment using liquid droplets can include electrical and plasmon modalities. For example, a set of droplets can be placed on a bottom substrate. A top substrate can be placed upon the droplets, which uses the droplets to align the substrates. Using the droplets in a capacitive or plasmon coupling modality, information or power can be transferred between the substrates using the droplets.
Type:
Grant
Filed:
October 29, 2014
Date of Patent:
February 6, 2018
Assignee:
Elwha LLC
Inventors:
William David Duncan, Roderick A. Hyde, Jordin T. Kare, Thomas M. McWilliams, Thomas Allan Weaver, Lowell L. Wood, Jr.
Abstract: A wireless headset supports simultaneous connections to two or more audio sources and can concurrently output audio from the different sources. The audio may include voice and/or audio playback, e.g., music playback. The wireless headset includes a first transceiver configured to receive a first audio input from a first source, a second transceiver configured to receive a second audio input from a second source, and an audio mixer configured to combine the first and second audio inputs into output audio.
Abstract: A backside-illuminated photodetector structure comprising a first reflecting region, a second reflecting region and a semiconductor region. The semiconductor region is between the first reflecting region and the second reflecting region. The semiconductor region comprises a first doped region and a second doped region.
Abstract: A light-emitting device comprises a light-emitting structure capable of emitting a light; an electrode formed on a side of the light-emitting structure; a transparent structure formed on a second side of the light-emitting structure, wherein the transparent structure is aligned to a region of the electrode, and comprises a first transparent layer and a second transparent layer around the first transparent layer; a contact structure formed on the second side of the light-emitting structure; and a reflective layer covering the transparent structure and the contact structure.
Abstract: A semiconductor device includes a p-type metal oxide semiconductor device (PMOS) and an n-type metal oxide semiconductor device (NMOS) disposed over a substrate. The PMOS has a first gate structure located on the substrate, a carbon doped n-type well disposed under the first gate structure, a first channel region disposed in the carbon doped n-type well, and activated first source/drain regions disposed on opposite sides of the first channel region. The NMOS has a second gate structure located on the substrate, a carbon doped p-type well disposed under the second gate structure, a second channel region disposed in the carbon doped p-type well, and activated second source/drain regions disposed on opposite sides of the second channel region.
Type:
Grant
Filed:
November 15, 2013
Date of Patent:
January 9, 2018
Assignee:
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Abstract: Methods and apparatus entailing an interconnect structure comprising interconnect features disposed in dielectric material over a substrate. Each interconnect feature comprises an interconnect member and a via extending between the interconnect member and a conductive member formed within the dielectric material. A through-silicon-via (TSV) structure is formed laterally offset from the interconnect structure by forming a first portion of the TSV structure with a first conductive material and forming a second portion of the TSV structure with a second conductive material. Forming the second portion of the TSV structure occurs substantially simultaneously with forming one of the interconnect features.
Abstract: An electronic device includes a semiconductor memory unit that includes: a gate including at least a portion buried in a substrate; a junction portion formed in the substrate on both sides of the gate; and a memory element coupled with the junction portion on one side of the gate, wherein the junction portion includes: a recess having a bottom surface protruded in a pyramid shape; an impurity region formed in the substrate and under the recess; and a contact pad formed in the recess.
Abstract: The present invention provides a light emitting apparatus comprising a three-color light emitting device unit including at least three light emitting diode (LED) chips for respectively emitting red, green and blue light; a white light emitting device unit including at least one blue LED chip with a fluorescent substance formed thereon; and a substrate provided with a first electrode connected in common to ends of the LED chips and second electrodes formed to correspond respectively to the LED chips.
Abstract: A semiconductor device includes a substrate and a plurality of storage nodes on the substrate and extending in a vertical direction relative to the substrate. A lower support pattern is in contact with the storage nodes between a bottom and a top of the storage nodes, the lower support pattern spaced apart from the substrate in the vertical direction, and the lower support pattern having a first maximum thickness in the vertical direction. An upper support pattern is in contact with the storage nodes above the lower support pattern relative to the substrate, the upper support pattern spaced apart from the lower support pattern in the vertical direction, and the lower support pattern having a second maximum thickness in the vertical direction that is greater than the first maximum thickness of the lower support pattern.
Abstract: Hydroxyl moieties are formed on a surface over a semiconductor substrate. The surfaces are silylized to replace the hydroxyl groups with silyl ether groups, the silyl ether groups being of the form: —OSiR1R2R3, where R1, R2, and R3 are each hydrocarbyl groups comprising at least one carbon atom. Silylation protects the wafers from forming defects through hydrolysis while the wafers are being transported or stored under ambient conditions.
Abstract: This improved, fluctuation resistant FinFET, with a doped core and lightly doped epitaxial channel region between that core and the gate structure, is confined to the active-gate span because it is based on a channel structure having a limited extent. The improved structure is capable of reducing FinFET random doping fluctuations when doping is used to control threshold voltage, and the channel structure reduces fluctuations attributable to doping-related variations in effective channel length. Further, the transistor design affords better source and drain conductance when compared to prior art FinFETs. Two representative embodiments of the key structure are described in detail.
Abstract: A semiconductor device is provided with a first oxide semiconductor film over an insulating surface; a second oxide semiconductor film over the first oxide semiconductor film; a third oxide semiconductor film in contact with a top surface of the insulating surface, a side surface of the first oxide semiconductor film, and side and top surfaces of the second oxide semiconductor film; a gate insulating film over the third oxide semiconductor film; and a gate electrode in contact with the gate insulating film and faces the top and side surfaces a of the second oxide semiconductor film. A thickness of the first oxide semiconductor film is larger than a sum of a thickness of the third oxide semiconductor film and a thickness of the gate insulating film, and the difference is larger than or equal to 20 nm.
Type:
Grant
Filed:
March 1, 2016
Date of Patent:
December 19, 2017
Assignee:
Semiconductor Energy Laboratory Co., Ltd.
Abstract: A method of concurrently forming source/drain contacts (CAs) and gate contacts (CBs) and device are provided. Embodiments include forming metal gates (PC) and source/drain (S/D) regions over a substrate; forming an ILD over the PCs and S/D regions; forming a mask over the ILD; concurrently patterning the mask for formation of CAs adjacent a first portion of each PC and CBs over a second portion of the PCs; etching through the mask, forming trenches extending through the ILD down to a nitride capping layer formed over each PC and a trench silicide (TS) contact formed over each S/D region; selectively growing a metal capping layer over the TS contacts formed over the S/D regions; removing the nitride capping layer from the second portion of each PC; and metal filling the trenches, forming the CAs and CBs.
Abstract: A semiconductor structure includes a die including a top surface and a sidewall, and a molding surrounding the die and including a top surface, a sidewall interfacing with the sidewall of the die, and a curved surface including a curvature greater than zero and coupling the sidewall of the molding with the top surface of the molding.
Type:
Grant
Filed:
February 27, 2014
Date of Patent:
December 5, 2017
Assignee:
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.