Abstract: A system and method for providing a single mode VCSEL (vertical cavity surface emitting laser) component (100) is disclosed, comprising a semiconductor substrate (102) having a lower surface and an upper surface, a bottom electrical contact (104) disposed along the lower surface of the substrate, a lower mirror (106) formed of n-type material and disposed upon the upper surface of the substrate, an active region (108) having a plurality of quantum wells disposed upon the lower mirror portion, an upper mirror (110) formed from isotropic material and disposed upon the active region, an equipotential layer (112) disposed upon the upper mirror portion, a first upper electrical contact (120) disposed upon the equipotential layer, a second upper electrical contact (122) disposed upon the equipotential layer at a particular distance (124) from the first upper electrical contact, a first isolation region (126) disposed beneath the first upper contact and traversing the equipotential layer, the upper mirror, the activ

Abstract: A titanium layer is formed on a substrate with chemical vapor deposition (CVD). First, a seed layer is formed on the substrate by combining a first precursor with a reducing agent by CVD. Then, the titanium layer is formed on the substrate by combining a second precursor with the seed layer by CVD. The titanium layer is used to form contacts to active areas of substrate and for the formation of interlevel vias.

Abstract: A process and structure for fabricating a non-volatile memory cell through the formation of a source and drain region and a charge trapping layer located therebetween is presented. E-fields for generating trapped charges are formed through using poly-edge discharge techniques wherein the gate structures of the memory cells are laterally separated from the vertical region of the source and drain regions. The gate structure forms a laterally directed e-field through the charge trapping layer to one of the source and drain regions which enables the charge to be trapped and retained in an area that is lateral to the source and drain regions. Lateral separation of the gate from the source and drain regions is maintained through the use of spacers which may take the form of insulated polysilicon structures or in an alternate embodiment may take the form of insulating spacers located on the sidewalls of the gate structure.

Abstract: An N+ buried diffusion region is formed between a P? silicon substrate and an N? epitaxial layer and a P+ buried diffusion region is formed between the N+ buried diffusion region and the N? epitaxial layer. An N diffusion region, a P diffusion region and an N diffusion region are formed in the surface for the N? epitaxial layer. The surface of the P+ buried diffusion region located, approximately, beneath the N diffusion region is recessed so as to go far away from the N diffusion region and a narrowed part is formed in this part. Thereby, in the OFF condition, the depletion layer further extends in the part where the narrowed part is formed. As a result, the withstanding voltage of the semiconductor device is increased.

Abstract: A semiconductor laser device includes a semiconductor laser chip, and a molded resin having a light diffusion capability. The semiconductor laser chip is covered with the molded resin.

Abstract: A method of forming resistance changing elements with improved operational characteristics for use in memory devices and the resulting structures are disclosed. A chalcogenide glass having the formula (Gex1Se1-x1)1-y1Agy1, wherein 18?x1?28, or the formula (Gex2Se1-x2)1-y2Agy2, wherein 39?x2?42, and wherein in both the silver is in a concentration which maintains the germanium selenide glass in the glass forming region is used in a memory cell. The glass may also have a glass transition temperature (Tg) near or higher than typical temperatures used for fabricating and packaging memory devices containing the memory cell.

Abstract: A light emitting device includes several LEDs, mounted on a shared submount, and coupled to circuitry formed on the submount. The LEDs can be of the III-Nitride type. The architecture of the LEDs can be either inverted, or non-inverted. Inverted LEDs offer improved light generation. The LEDs may emit light of the same wavelength or different wavelengths. The circuitry can couple the LEDs in a combination of series and parallel, and can be switchable between various configurations. Other circuitry can include photosensitive devices for feedback and control of the intensity of the emitted light, or an oscillator, strobing the LEDs.

Abstract: A high-voltage transistor with a low specific on-state resistance and that supports high voltage in the off-state includes one or more source regions disposed adjacent to a multi-layered extended drain structure which comprises extended drift regions separated from field plate members by one or more dielectric layers. With the field plate members at the lowest circuit potential, the transistor supports high voltages applied to the drain in the off-state. The layered structure may be fabricated in a variety of orientations. A MOSFET structure may be incorporated into the device adjacent to the source region, or, alternatively, the MOSFET structure may be omitted to produce a high-voltage transistor structure having a stand-alone drift region.

Abstract: A pixel site of a semiconductor imager structure includes a substrate layer of a first dopant type; a photodiode being formed of a doped well region within the substrate layer, the doped well region being of a second dopant type; a transistor wherein a terminal of the transistor being provided within the doped well region, the terminal of the transistor being of the second dopant type and of a dopant concentration greater than a dopant concentration of the doped well region; and an oxide layer formed over the substrate layer, the doped well region, and the terminal of the transistor. The oxide layer has a varying height such that a height of the oxide layer associated with the doped well region is thicker than a height of the oxide layer associated with the terminal of the transistor. The oxide layer includes a step region being located where the height of the oxide layer transitions from the height associated with the doped well region to the height associated with the terminal of the transistor.

Abstract: An apparatus comprising a volume of memory material and a pair of spacedly disposed conductors. An electrode coupled to the volume of memory material and disposed between the volume of memory material and one conductor comprises a first material having a first resistivity value and a second material having a different second resistivity value formed by exposing the first material to a gaseous ambient.

Abstract: A metallic element is effectively removed from a semiconductor film crystallized by using the metallic element. The concentration distribution of phosphorous or antimony in the depth direction of at least one of a source and a drain of a TFT semiconductor film has: a region in which the concentration is 1×1020 atoms/cm3 or less is 5 nm or greater in thickness, and 5×1019 atoms/cm3 or greater in the maximum value. By creating this concentration distribution, and by thermal annealing at about between 500 and 650° C., the metallic element within a channel forming region diffuses to the source or the drain, and at the same time as gettering is accomplished, the region in which the concentration is 1×1020 atoms/cm3 or less is made into a nucleus and the source region/drain region is recrystallized.

Abstract: A portable information apparatus has a film liquid crystal device having a pair of flexible substrates spaced apart from one another to define therebetween a gap containing liquid crystal, first surface portions having a curved cross-section, engagement portions extending from respective ones of the first surface portions, and at least one second surface portion having a planar cross-section. An injection port is formed in the at least one second surface portion and through which the liquid crystal is injected into the gap. A sealing portion is disposed on the at least one second surface portion for sealing the injection port. A holding structure has a first holding member and a second holding member for holding the film liquid crystal device in a curved state while the at least one second surface portion of the film liquid crystal device remains planar in cross-section and while the first holding member engages the engagement portions of the liquid crystal device.

Abstract: An apparatus having a circuit coupled to the gate contact of field effect transistor wherein the transistor's gate includes a dielectric layer of which at least a portion is an organic dielectric. The circuit is configured to produce one or more storage voltage pulses that cause charge to be stored in the dielectric layer. The field effect transistor has a semiconductor layer with a conductive path whose conductivity changes for a given Vg in response to storing the charge. The circuit may produce one or more dissipation voltage pulses having a voltage of opposite sign to the one or more storage pulses, that cause dissipation of charge stored in the dielectric layer. Further disclosed are a memory and a method of electronically storing and reading information, both utilizing the organic-based polarizable gate transistor apparatus.

Abstract: There is provided a photoelectric converter comprising a photoelectric conversion element of a laminated structure comprising a first electrode layer, an insulation layer for blocking the passage of a first carrier and a second carrier, a photoelectric conversion semiconductor layer, an injection blocking layer for blocking the injection of the first carrier to the photoelectric conversion semiconductor layer, and a second electrode layer, wherein a switching means is provided for operating the converter by switching the following three operation modes a) through c) for applying an electric field to each layer of the photoelectric conversion element; a) an idling mode for emitting the second carrier from the photoelectric conversion element, b) a refreshment mode for refreshing the first carrier accumulated in the photoelectric conversion element, and c) a photoelectric conversion mode for generating pairs of the first carrier and the second carrier in accordance with an amount of incident light to accumulate

Abstract: An improved cell layout for a C3MOS circuit with inductive broadbanding positions the inductor at a distance from the active region to improve isolation and aligns the edges of the resistor, inductor, and transistor regions near the common edge of adjacent cells to decrease the length of the cell-to-cell interconnect lines.

Abstract: On a silicon substrate 201, there are formed a silicon oxide 202, an adhesion layer 203 consisting of TiO2, a lower electrode 204 consisting of Pt, a ferroelectric thin film 205, and an upper electrode 206 consisting of Pt. A portion of the ferroelectric thin film adjacent to the upper electrode 206 is formed from a compound with a composition formula of SrBi2 (TaxNb1-x)2O9 where x=0.7. A compound with a value x in the composition formula being greater than 0.7 is used for the portion of the ferroelectric thin film adjacent to the upper electrode 206, so as to generate an appropriate number of grain boundaries on the surface of the ferroelectric film 205, the grain boundaries enabling implementation of anchoring effect between the ferroelectric film 205 and the upper electrode 206, thereby achieving prevention of exfoliation of the upper electrode 206 from the ferroelectric film 205.

Abstract: A polymer-based or silicon-based accumulation type, depletion mode field effect transistor, suitable as a driver for load. Optionally, the load is another accumulation type, depletion mode field effect transistor. The transistor may be of the TFT type, either lateral or vertical. Optionally, it may have Schottky diode contacts to source and drain electrodes, possibly with a reverse biased Schottky junction, or it may have a negatively charged gate dielectric.

Abstract: A semiconductor wafer made from silicon which is doped with hydrogen. The hydrogen concentration is less than 5*1016 atcm?3 and greater than 1*1012 atcm?3. A method for producing a semiconductor wafer from silicon includes separating the semiconductor wafer from a silicon single crystal, with the single silicon crystal being pulled from a melt, in the presence of hydrogen, using the Czochralski method. The hydrogen partial pressure during the pulling of the single silicon crystal is less than 3 mbar.

Abstract: A semiconductor wafer with variable transmittance, serves as a saturable absorber for performing passive Q-switching in a laser system to produce laser pulses having defined output characteristics. By translating or rotating the semiconductor saturable absorber, loss properties of a laser cavity may be altered. In this manner, the output characteristics of the laser pulses can be varied without changing other parameters of laser operation. The output characteristics may include pulse duration, pulse repetition rate, peak power and average output power of the laser pulses. The semiconductor wafer can be made of doped or undoped GaAs, AlGaAs, InP, etc. Furthermore, the tunable Q-switch may simultaneously serve as an output coupler for the laser cavity.

Abstract: A GaN-based composition semiconductor light-emitting element and its window layer structure includes a substrate where several epitaxy layers are sequentially formed and a window layer formed on the epitaxy layers so as to construct a light-emitting element. Each of the epitaxy layers and the window layer is composed of GaN-based composition. Boron atoms are doped in the window layer so as to increase the band gap of the window layer and decrease the refractive index. By appropriately doping the boron atoms, the activity rate of the P-type will be increased so as to increase the electric conductivity. Furthermore, by increasing the thickness of the window layer, the probability of defect generation can be reduced.