Abstract: A semiconductor integrated circuit device has a plurality of design patterns composed of circuit elements or wires formed on a substrate. The respective finished sizes of the plurality of design patterns have a plurality of minimum size values which differ from one design pattern to another depending on the geometric feature of each of the design patterns.

Abstract: Integrated circuits are tested on the wafer level through an additional circuit part that is electrically connected via at least one connecting line with the associated integrated circuit. The additional circuit part is integrated into an interspace between the integrated circuits of the wafer. Functions of the integrated circuit can be controlled via the connecting line. For example, in the case of a memory module such as a DRAM, internal voltages and/or currents of the integrated circuit can advantageously be measured even on internal lines which are otherwise only accessible with difficulty. Following the wafer-level testing and dicing of the integrated circuits into individual chips, the additional circuit part becomes unusable.

Abstract: A high-voltage transistor with a low specific on-state resistance and that supports high voltage in the off-state includes one or more source regions disposed adjacent to a multi-layered extended drain structure which comprises extended drift regions separated from field plate members by one or more dielectric layers. With the field plate members at the lowest circuit potential, the transistor supports high voltages applied to the drain in the off-state. The layered structure may be fabricated in a variety of orientations. A MOSFET structure may be incorporated into the device adjacent to the source region, or, alternatively, the MOSFET structure may be omitted to produce a high-voltage transistor structure having a stand-alone drift region.

Abstract: Embodiments concern contacts for use in integrated circuits, and methods of their manufacture, which result in a reduced likelihood of shorting between unrelated portions of an overlying conductive layer across misaligned contacts. Embodiments of the method involve performing a first etching process to pattern the conductive layer, where the etching compound used in the first etching process is relatively selective to the conductive layer's materials. Embodiments of the method also involve performing a second, contact related etching process that removes a portion of any misaligned contacts that were exposed by the first etching process, where the etching compound used in the second etching process is selective to the contacts' materials. The embodiments of the method could be used to form vias and other interconnect structures as well.

Abstract: A method for generating electrically conducting and/or semiconducting structures in three dimensions in a matrix that includes two or more materials in spatially separated material structures is disclosed. An electric field is applied to the separate material structure and the field is modulated spatially according to a protocol. The protocol represents a predetermined pattern of electrically conducting and/or semiconducting structures that are generated in the material structure in response to the field. The matrix composed by the material structures includes structures of this kind in three dimensions.

Abstract: A trench MOSFET transistor device and method of making the same are provided. The trench MOSFET transistor device comprises: (a) a drain region of first conductivity type; (b) a body region of a second conductivity type provided over the drain region, such that the drain region and the body region form a first junction; (c) a source region of the first conductivity type provided over the body region, such that the source region and the body region form a second junction; (d) source metal disposed on an upper surface of the source region; (e) a trench extending through the source region, through the body region and into the drain region; and (f) a gate region comprising (i) an insulating layer, which lines at least a portion of the trench and (ii) a conductive region, which is disposed within the trench adjacent the insulating layer. The body region in this device is separated from the source metal.

Abstract: A method of fabricating shallow trench isolation. In the method, a refill step of oxide layer and a step of forming a sacrificial layer on the semiconductor substrate are applied after filling insulating layer into the shallow trenches. The purpose of the steps is to protect the oxide layer on the semiconductor substrate and the corner of the shallow trenches, used to isolate the STI.

Abstract: Large area silicon carbide devices, such as light-activated silicon carbide thyristors, having only two terminals are provided. The silicon carbide devices are selectively connected in parallel by a connecting plate. Silicon carbide thyristors are also provided having a portion of the gate region of the silicon carbide thyristors exposed so as to allow light of an energy greater than about 3.25 eV to activate the gate of the thyristor. The silicon carbide thyristors may be symmetric or asymmetrical. A plurality of the silicon carbide thyristors may be formed on a wafer, a portion of a wafer or multiple wafers. Bad cells may be determined and the good cells selectively connected by a connecting plate.

Abstract: A memory array including a bit cell row, a strap cell row, a first power supply line, and a first offset supply line is provided. The bit cell row may include a bit cell that includes a first transistor disposed in a first bit cell body region. The first transistor may include a first active region. The strap cell row may include a strap cell that includes a first strap cell body region. The first strap cell body region may be conductively coupled to the first bit cell body region. The first power supply line may be electrically coupled to the first active region and may provide a first supply voltage potential to the first active region. The first offset supply line may be electrically coupled to the first strap cell body region and may provide a first offset voltage potential to the first bit cell body region via the first strap cell body region. The first supply voltage potential is operable to be different from the first offset voltage potential.

Abstract: A protection circuit including a power supply terminal supplied with a power supply potential, a reference terminal supplied with a reference potential, and a first p-channel MOS transistor having a first gate, a first source, a first drain and a first back gate. The first gate, the first source and the first back gate are connected to the power supply terminal. Also included is a second p-channel MOS transistor having a second gate, a second source, a second drain and the first back gate, in which the second source of the second p-channel MOS transistor is connected to the first drain of the first p-channel MOS transistor, and the second gate and the second drain of the second p-channel MOS transistor is connected to the reference terminal.

Abstract: A thick film millimeter wave transceiver module includes a base plate and a multi-layer substrate board having a plurality of layers of low temperature transfer tape received on the base plate. The different layers can vary. They can include a DC signals layer having signal tracks in connection; a ground layer having ground connections; a device layer having capacitors and resistors embedded therein; and a top layer having cut-outs for receiving MMIC chips therein. A solder preform layer is located between the device layer and the top layer for securing any MMIC chips. A channelization plate is received over the multi-layer substrate board and a channel is formed to receive MMIC chips and provide isolation between transmit and receive signals.

Abstract: A power device having a multi-chip package structure and a manufacturing method therefor are provided. In the power device, a transistor, which is a switching device, and a control integrated circuit (IC) chip, which is a driving device, are mounted together in a package, thereby requiring a high insulation withstand voltage between the transistor chip and the control IC chip. The power device and the manufacturing method can simplify a packaging process by attaching the control IC chip on a chip pad of a lead frame using an insulating adhesive tape at a level with the transistor chip. Furthermore, the overall size of a package in the power device can be reduced by attaching the control IC chip on top of the transistor chip using the insulating adhesive tape. In the case of attaching the control IC chip on the top of the transistor chip, a liquid non-conductive adhesive can be used instead of an insulating adhesive tape.

Abstract: A semiconductor device with a capacitor having a charge retaining capability improved by preventing generation of a leakage current in a capacitor dielectric film, and a manufacturing method of the same are provided. An indium oxide film is formed to continuously cover the upper surfaces of a tungsten film and an interlayer oxide film. A tantalum oxide film is formed to continuously cover the surface of the indium oxide film and a portion of the upper surface of the interlayer oxide film. Another indium oxide film is formed to cover the upper surface of the tantalum oxide film.

Abstract: A method for forming a back-side contact for a vertical trench device includes grinding a back-side of a semiconductor substrate, milling a trench in the back-side of the semiconductor substrate, wherein a vertical trench fill is exposed, and depositing a conductive material, wherein the conductive material shorts the vertical trench fill to a buried plate. Grinding the back-side of the semiconductor substrate further includes grinding a dimple beneath a portion of the vertical trench device, wherein the trench is milled in the bottom portion of the dimple.

Abstract: An interconnect structure including a patterned multilayer of spun-on dielectrics as well as methods for manufacturing the same are provided. The interconnect structure includes a patterned multilayer of spun-on dielectrics formed on a surface of a substrate. The patterned multilayer of spun-on dielectrics is composed of a bottom low-k dielectric, a buried etch stop layer, and a top low-k dielectric, wherein the bottom and top low-k dielectrics have a first composition, the said buried etch stop layer has a second composition which is different from the first composition and the buried etch stop layer is covalently bonded to said top and bottom low-k dielectrics. The interconnect structure further includes a polish stop layer formed on the patterned multilayer of spun-on dielectrics; and metal conductive regions formed within the patterned multilayer of spun-on dielectrics.

Abstract: A clock signal generator in an integrated circuit semiconductor device and a method of generating a clock signal, the clock signal generator comprising: a semiconductor substrate (2); an oscillator unit (4) which comprises at least one support member (10, 12) which is fixed relative to the substrate (2), an oscillator arm (6) which is oscillatably disposed to the at least one support member (10, 12) with regard a reference position, which oscillator arm (6) includes first and second conductive sections (6a, 6b) at positions extended from the at least one support member (10, 12), and at least one biasing element (14, 16) for biasing the oscillator arm (6) towards the reference position; a driver (18) which is disposed at the substrate (2) in spaced relation adjacent one of the conductive sections (6a) of the oscillator arm (6), which driver (18) is configured in use to drive the one of the conductive sections (6a) of the oscillator arm (6) towards or away therefrom when an electrical signal is applied thereto;

Abstract: A composite light-emitting device according to the present invention includes a light-emitting element including a transparent substrate and a multilayer structure formed on the substrate. The multilayer structure includes first and second semiconductor layers of first and second conductivity types, respectively. The device further includes a submount member for mounting the light-emitting element thereon. The principal surface of the submount member faces the multilayer structure. The submount member is electrically connected to the light-emitting element. The light-emitting element is covered with a wavelength-shifting resin member. The resin member is provided on the principal surface of the submount member and contains a photofluorescent or filtering compound. The photofluorescent compound shifts the wavelength of radiation that has been emitted from the light-emitting element, while the filtering compound partially absorbs the radiation.

Abstract: A layout method is provided for a latch-up prevention circuit of a semiconductor memory device which includes the steps of: arranging a cell array at substantially the middle of the device; placing peripheral circuits next to both sides of the cell array; placing a plurality of pads on both sides of the cell array between the peripheral circuits and both edges of the device; and arranging guard rings beneath the plurality of pads. The layout method further includes a plurality of ESD protection transistors disposed axially along the direction as the plurality of pads between the plurality of pads and an edge of the device. And each of guard ring is a NWELL guard ring, and connected to a supply voltage and ground.

Abstract: A corona preionization electrode unit for use in gas laser apparatus, wherein the electric field for corona discharge is concentrated, and ultraviolet radiation is not blocked, and further the laser gas stream is not obstructed, thereby allowing efficient, stable and uniform corona preionization. The corona preionization electrode unit is disposed in a gas laser apparatus together with a pair of main discharge electrodes for ionizing and exciting a laser gas. The corona preionization electrode unit includes a first electrode covered with a dielectric material and a second electrode placed in contact with the outer surface of the dielectric material around the first electrode. The corona preionization electrode unit is positioned in the vicinity of either one of the main discharge electrodes. The second electrode is a plate-shaped member having a straight edge contacting at least the outer surface of the dielectric material.

Abstract: Vertical power devices include a semiconductor substrate having a drift region of first conductivity type therein and first and second stripe-shaped trenches that extend in the semiconductor substrate and define a drift region mesa therebetween. First and second insulated source electrodes are provided in the first and second stripe-shaped trenches, respectively. A UMOSFET, comprising a third trench that is shallower than the first and second stripe-shaped trenches, is provided in the drift region mesa.