Patents Examined by John B. Vigushin
  • Patent number: 7203068
    Abstract: An electronic apparatus according to the present invention includes two modules which decode high frequency analog signals. Furthermore, each of the modules is provided with an RF section at a position away from the center of the module in either longitudinal direction to carry out radio communications using high frequencies. In this electronic apparatus, the two modules are arranged so that their longitudinal sides extend parallel with each other in opposite directions. The two modules are also misaligned with each other in the longitudinal direction so that the RF sections lie away from each other and so that connectors to which signals subject to noise interference are inputted lie away from each other.
    Type: Grant
    Filed: December 23, 2003
    Date of Patent: April 10, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hironori Motoe
  • Patent number: 7203073
    Abstract: A group of bus bars, forming a power circuit, are adhesively bonded to a surface of a control circuit board. Surface-mounting type relay switches are used as a switching unit for the power circuit. Contact-side terminals of each relay switch are mounted on the bus bar group while coil-side terminals thereof are mounted on the control circuit board. The opening and closing of relay contacts are controlled by a control circuit incorporated in the control circuit board.
    Type: Grant
    Filed: July 1, 2003
    Date of Patent: April 10, 2007
    Assignees: Autonetworks Technologies, Ltd., Sumitomo Wiring Systems, Ltd., Sumitomo Electric Industries, Ltd.
    Inventors: Shinji Kawakita, Takahiro Onizuka
  • Patent number: 7203074
    Abstract: Electronic Circuit Building Blocks are mechanically connected to each other to form larger circuit boards using a mechanical bridge connector. The Electronic Circuit Building Blocks include female interlocking elements formed on its edges, and the mechanical bridge connector includes male interlocking elements. Half parts of the male interlocking elements of the mechanical bridge connector are inserted into the corresponding female interlocking elements of the Electronic Circuit Building Blocks from one side of the circuit board. The Electronic Circuit Building Blocks include through-holes for mounting through-hole components and/or surface-mount pads for mounting surface-mount components. The Electronic Circuit Building Blocks also include traces interconnecting two or more of the through-hole components and the surface-mount components.
    Type: Grant
    Filed: December 16, 2003
    Date of Patent: April 10, 2007
    Assignee: Intellect Lab, LLC
    Inventors: Andrew Yaung, Neal S. Greenberg, Che Wai Yeung
  • Patent number: 7198866
    Abstract: A plurality of single cells 10a to 10d, each being packaged by laminate films 12 and 13, are attached onto one surface of a flexible printed circuit board 20, in a state of being interconnected in series to each other, by the use of a double faced tape. Single cells 10a? to 10d? are attached in a similar way onto the other surface of the flexible printed circuit board 20. Each group of the cells on the both surfaces of the flexible printed circuit board 20 are interconnected in parallel. Voltage detection lines 30a to 30e are wired on the flexible printed circuit board 20. Positive and negative electrode tabs 14 and 15 of the respective single cells are connected to the respectively corresponding voltage detection lines 30a to 30e through connection terminals 31a to 31e provided on the flexible printed circuit board 20.
    Type: Grant
    Filed: July 2, 2003
    Date of Patent: April 3, 2007
    Assignee: Nissan Motor Co., Ltd.
    Inventors: Takeshi Miyamoto, Yuji Nakada
  • Patent number: 7190594
    Abstract: A connector is provided for simultaneously improving both the NEXT high frequency performance when low crosstalk plugs are used and the NEXT low frequency performance when high crosstalk plugs are used. The connector includes a first compensation structure provided on an inner metalized layer of the PCB at a first stage area of the PCB, and a second compensation structure, provided at a second stage area of the PCB, for increasing compensation capacitance with increasing frequency.
    Type: Grant
    Filed: May 14, 2004
    Date of Patent: March 13, 2007
    Assignee: Commscope Solutions Properties, LLC
    Inventors: Amid Hashim, Julian Robert Pharney
  • Patent number: 7187559
    Abstract: This invention is a circuit board device having a filter element. It has a base board (4), a circuit part (2) mounted on the base board (4), a filter element (5) arranged between the circuit part (2) and the base board (4), and a semiconductor component (3) mounted on the same plate as the circuit part (2) on the base board (4). The semiconductor component (3) is mounted on a thin plate region (17) that is thinner than a thick plate region (16) having its thickness increased by mounting the circuit part (2) on the base board (4). Thus, the thickness of the whole circuit board device is reduced and the filter element (5) is covered with a sufficiently thick dielectric insulating material so as to prevent deterioration in filter characteristic.
    Type: Grant
    Filed: December 4, 2002
    Date of Patent: March 6, 2007
    Assignee: Sony Corporation
    Inventors: Takayuki Hirabayashi, Akihiko Okubora
  • Patent number: 7176579
    Abstract: The present invention realizes the miniaturization of a semiconductor module. The semiconductor module includes a module board having external electrode terminals and a heat radiation pad over a lower surface thereof, a first semiconductor chip incorporating an initial-stage transistor of a high frequency power amplifying device therein, a second semiconductor chip incorporating a next-stage transistor and a final-stage transistor therein, and an integrated passive device which constitutes a matching circuit. At least one of the first semiconductor chip and the second semiconductor chip and the integrated passive device are mounted over an upper surface of the module board in an overlapped manner.
    Type: Grant
    Filed: December 12, 2003
    Date of Patent: February 13, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Satoru Konishi, Tsuneo Endoh, Hirokazu Nakajima, Masaaki Tsuchiya
  • Patent number: 7170757
    Abstract: One embodiment of a field changeable graphics system for a computing device includes a graphics card and an interface assembly. The interface assembly is adapted to interface the graphics card with the motherboard of a computing device, without directly mounting the graphics card to the motherboard. One advantage of the disclosed graphics system is that it enables a computing device user to upgrade the existing device's graphics system. Thus, the user is not forced to purchase an entirely new computing device in order to take advantage of graphics innovations. This advantage is particularly significant for users of portable computing devices, such as laptop computers and PDAs.
    Type: Grant
    Filed: April 9, 2004
    Date of Patent: January 30, 2007
    Assignee: NVIDIA Corporation
    Inventors: Daniel J. Driscoll, Joseph D. Walters, Craig E. Dowdall, Charles E. Buffington
  • Patent number: 7167378
    Abstract: At least one of a feedback path and a feed path is divided into two paths, and the divided feedback path and the feed path for feeding a signal form a twisted pattern to suppress radiation noise of a high frequency by a twisted pair effect. The other divided feedback path decreases a resistance value of a direct current component and decreases a whole direct current resistance to feed a sufficient current to the path.
    Type: Grant
    Filed: November 4, 2004
    Date of Patent: January 23, 2007
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Shinji Yamada
  • Patent number: 7167376
    Abstract: A multilayer wiring board on which multiple components are overlappingly mounted. The multilayer wiring board includes: a first surface on which a first component among the multiple components is mounted; and a second surface whose height in a thickness direction of the multilayer wiring board is smaller than that of the first surface, by which a step is provided between the first surface and the second surface, a second component among the multiple components being mounted on the second surface to partially overlap the first component in a non-contact manner, the second surface also having a light-transmitting window through which light is transmitted.
    Type: Grant
    Filed: May 14, 2004
    Date of Patent: January 23, 2007
    Assignee: Fuji Photo Film Co., Ltd.
    Inventors: Mamoru Miyashita, Hiroki Ohta
  • Patent number: 7167373
    Abstract: One embodiment of the invention includes a flexible circuit and a stiffener. The flexible circuit has first, second, and third portions. The first portion is folded on an upper surface of the third portion and has first contact elements attached to a first device. The second portion is folded on the first device and has second contact elements attached to a second device. The stiffener is attached to the upper surface of the third portion and located between the upper surface of the third portion and the first portion.
    Type: Grant
    Filed: March 8, 2004
    Date of Patent: January 23, 2007
    Assignee: Virtium Technology, Inc.
    Inventors: Phan Hoang, Chinh Nguyen, Frank Hoang, Andy Le
  • Patent number: 7161088
    Abstract: A system, method and apparatus for providing a printed circuit board having optimized power delivery planes and signal routing regions are disclosed. In one aspect, the present disclosure teaches a printed circuit board having two or more cores coupled together using a prepreg sheet having selected regions of increased permittivity. In combining the cores with the prepreg sheet, the regions of increased permittivity are preferably aligned with power delivery planes defined between respective cores. By increasing the permittivity within the power delivery planes, the greater the reduction in area of the cores needed for power delivery and the greater the area retained on the cores for providing signal routing. As a result, a printed circuit board incorporating teachings of the present disclosure may support more advanced and complex information handling system implementations.
    Type: Grant
    Filed: December 4, 2003
    Date of Patent: January 9, 2007
    Assignee: Dell Products L.P.
    Inventor: Joseph R. Nicolaisen
  • Patent number: 7158383
    Abstract: A technique for fabricating a resistor on a flexible substrate. Specifically, at least a portion of a polyimide substrate is activated by exposure to a ion sputter etch techniques. A metal layer is disposed over the activated portion of the substrate, thereby resulting in the formation of a highly resistive metal-carbide region. Interconnect layers are disposed over the metal-carbide region and patterned to form terminals at opposite ends of the metal carbide region. The metal-carbide region is patterned to form a resistor between the terminals. Alternatively, only a selected area of the polyimide substrate is activated. The selected area forms the area in which the metal-carbide region is formed. Interconnect layers are disposed over the metal-carbide region and patterned to form terminals at opposite ends of the metal-carbide region.
    Type: Grant
    Filed: November 18, 2003
    Date of Patent: January 2, 2007
    Assignee: General Electric Company
    Inventors: Kevin M. Durocher, Richard J. Saia, Vikram B. Krishnamurthy
  • Patent number: 7152313
    Abstract: In some embodiments, an article of manufacture includes a metal layer and a first dielectric layer in contact with a first face of the metal layer. The article of manufacture also includes a second dielectric layer in contact with a second face of the metal layer. The second face of the metal layer is opposite to the first face of the metal layer. The metal layer may be a continuous sheet having slots formed therein to allow the first and second dielectric layers to adhere to each other by way of the slots.
    Type: Grant
    Filed: November 26, 2003
    Date of Patent: December 26, 2006
    Assignee: Intel Corporation
    Inventors: Dustin P. Wood, Mark E. Thurston, Mahadevan Suryakumar
  • Patent number: 7154758
    Abstract: The invention describes a method for producing chip cards with contactless and/or contact-type operation having a multilayer card body, an integrated circuit and at least one coil (2, 21) for data exchange and for power supply. The coil (2, 21) is applied to one or more layers (11) of the card body by printing technology, whereby after production of the printed coil a metal foil (4, 41) is placed over the coil terminals (32, 33) and laminated into the card body, thereby producing the connection between the contact areas (32, 33) of the printed coil and the metal foil (4, 41).
    Type: Grant
    Filed: May 7, 2002
    Date of Patent: December 26, 2006
    Assignee: Giesecke & Devrient GmbH
    Inventors: Ando Welling, Matthias Bergmann, Joachim Hoppe
  • Patent number: 7154047
    Abstract: A substrate (300) for a package of high frequency semiconductor devices comprising a planar insulating substrate having a plurality of parallel, planar metal layers (301a, 301b, etc.) embedded in the insulator. The substrate further has at least one pair of parallel, metal-filled vias (302 and 303) traversing the substrate; the vias have a diameter and a distance from each other of at least this diameter. The metal in each via has a sheet-like extension (321a, 321b, etc.) in each of selected planes of said metal layers, resulting in an increased via-to-via capacitance so that the reflection of a high frequency signal is less than 10%.
    Type: Grant
    Filed: February 27, 2004
    Date of Patent: December 26, 2006
    Assignee: Texas Instruments Incorporated
    Inventor: Gregory E. Howard
  • Patent number: 7154049
    Abstract: A printed circuit board providing crosstalk compensation. The printed circuit board includes first plated through holes for receiving a first connecting component and second plated through holes for receiving a second connecting component. A signal carrying trace transmits a signal from one of the first plated through holes to one of the second plated through holes. A phase delay control trace is in electrical connection with the one of the first plated through holes. The phase delay control trace affects phase delay of the signal from the one of the first plated through holes to the one of the second plated through holes.
    Type: Grant
    Filed: November 19, 2003
    Date of Patent: December 26, 2006
    Assignee: The Siemon Company
    Inventors: Brian Celella, Vito Pagliarulo, Daniel Mullin
  • Patent number: 7154759
    Abstract: In a mounting structure of an integrated circuit, an electrolytic capacitor for smoothing power of a heating element is disposed out of range of thermal effect of the heating element, and a ceramic capacitor for supplementing the operation of the electrolytic capacitor is additionally disposed between the electrolytic capacitor and the heating element. Accordingly, a long lifespan of the electrolytic capacitor and a stable operation of the heating element can be guaranteed.
    Type: Grant
    Filed: November 29, 2004
    Date of Patent: December 26, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Joong-kil Kwon
  • Patent number: 7148424
    Abstract: A disposable electronic device has a body constructed of juxtaposed lengths of an elongate, ribbon-like substrate of dielectric material secured together to establish a multiple-layered self-sustaining structure, and circuitry formed on the substrate. At least a portion of the circuitry is constructed of a deconstructable material which is deconstructed to render the device inoperative by at least one of the following: interrupting a securement of juxtaposed lengths of the substrate, exposing the deconstructable material to at least one of ambient conditions including ambient air, ambient light and ambient moisture, and reaching a predetermined accumulated amount of time during which the circuitry is operated. At least a portion of the substrate is constructed of deconstructable material which is deconstructed by exposure to at least one of the ambient conditions to render the device ready for disposal.
    Type: Grant
    Filed: October 5, 2001
    Date of Patent: December 12, 2006
    Assignee: Dynamic Technologies Corp.
    Inventors: Randice-Lisa Altschul, Lee S. Volpe
  • Patent number: 7145782
    Abstract: In one embodiment, the present invention includes a method of mounting a semiconductor device to a first side of a circuit board; and mounting at least one voltage regulator device to a second side of the circuit board, the second side opposite to the first side. The voltage regulator devices may be output filters, inductors, capacitors, and the like. In certain embodiments, the devices may be located directly underneath the semiconductor device.
    Type: Grant
    Filed: July 16, 2004
    Date of Patent: December 5, 2006
    Assignee: Intel Corporation
    Inventors: Damion Searls, Edward Osburn