Abstract: A back-to-back semiconductor device module including two semiconductor devices, the backs of each being secured to one another. Each of the bond pads of both of the semiconductor devices are disposed adjacent a single, mutual edge of the back-to-back semiconductor device module. The back-to-back semiconductor device module may be secured to a carrier substrate in a substantially perpendicular orientation relative to the former. A process for securing the back-to-back semiconductor device module directly to the carrier substrate may employ a solder reflow technique. Alternatively, a module-securing device may be employed to secure the back-to-back semiconductor device module to the carrier substrate. An embodiment of a module-securing device comprises an alignment device having one or more receptacles formed therein and intermediate conductive elements that are disposed within the receptacles to establish an electrical connection between the semiconductor devices and the carrier substrate.

Abstract: A fluorine-containing resin molded article can be obtained by putting it between smooth molds having a surface roughness (Ra) of not more than 50 .ANG. and compression-molding it under molding conditions of a molding temperature of 270.degree. to 340.degree. C., a molding pressure of not less than 10 kg/cm.sup.2 and compression time of not less than 2 minutes, to give smoothed fluorine-containing resin molded article having a surface roughness of not more than 500 .ANG.. Particles, metal impurities, organic impurities or the like are difficult to adhere to the surface of the article, and can be removed significantly by washing.

Abstract: An optoelectronic semiconductor component has a radiation-emitting active layer sequence which is associated with at least one poorly dopable semiconductor layer of a first conductivity type. A heavily doped first degenerated junction layer of a first conductivity type and a heavily doped second degenerated junction layer of a second conductivity type opposite to the first conductivity type are provided between the poorly dopable semiconductor layer and a contact layer of the semiconductor body, the contact layer being associated with the poorly dopable semiconductor layer.

Abstract: A MOSFET die and a Schottky diode die are each mounted within a device package on a common lead frame pad with their drain and cathode terminals, respectively, connected together at the common pad. The source terminal of the MOS gated device and the anode terminal of the Schottky diode are each electrically connected by wire bonds to an insulated pin, and the gate electrode of the MOS gated device is electrically connected by wire bonds to another pin. A redundant wire connection runs from the source terminal of the MOS gated device to the anode terminal of the Schottky diode reduce the inductance in the anode lead.

Abstract: There is provided a field effect transistor including a semi-insulating semiconductor substrate formed with a recess at a region in which a gate is to be formed, a gate base layer formed on the recess and composed of one of an InP layer and a plurality of layers including an InP layer, and a gate electrode formed on the gate base layer. The InP layer may be replaced with an InGaP layer, an Al.sub.X Ga.sub.1-X As (0.ltoreq.X.ltoreq.1) layer, an In.sub.X Ga.sub.1-X As (0.ltoreq.X.ltoreq.1) layer, or an In.sub.X Al.sub.1-X As (0.ltoreq.X<0.4 or 0.6<X.ltoreq.1) layer. The above-mentioned field effect transistor prevents thermal instability thereof caused by impurities such as fluorine entering a donor layer to thereby inactivate donor. As a result, there is presented a highly reliable compound field effect transistor.

Abstract: A MOSgated device has a plurality of rows of closed cells which each have a laterally enlarged central base area having two narrow oppositely extending base stripes. Each cell in the row is spaced from the adjacent cell in the row, and each cell of one row is nested into the cells of an opposite row such that its enlarged central region is longitudinally located adjacent the space between the cells of the adjacent row. The polysilicon gate is a continuous sheet and permits gate current to spread both longitudinally and laterally. The invention can be carried out with planar and groove technologies.

Abstract: The instant invention pertains to a multi-layer tamper proof electronic coating wherein the first layer is a protecting layer produced from a preceramic silicon containing material and at least one filler. The second layer is a resin sealer coat produced from a sealer resin selected from the group consisting of colloidal inorganic-based siloxane resins, benzocyclobutene based resins, polyimide polymers, siloxane polyimides and parylenes. An optional third layer is a cap coating layer selected from SiO.sub.2 coating, SiO.sub.2 /ceramic oxide coating, silicon containing coatings, silicon carbon containing coatings, silicon nitrogen containing coatings, silicon oxygen nitrogen coatings, silicon nitrogen carbon containing coatings and/or diamond like coatings.

Abstract: A method for packaging and protection of sensors, particularly so called microsensors is disclosed. A sensor unit (either a sensor chip or sensor package) is flip chip bonded to a substrate having a through hole, such that the sensing element is placed above the through hole. An underfill material is applied in such a way that due to capillary forces, the entire common area between the sensor and the substrate is completely filled, while the sensing element is not covered by the underfill material. This provides an effective way of sealing the sensing element from the side of the package containing the electronics. For a sensor chip that has been through a first level packaging process, the above mentioned method can still be used for bonding the sensor package to a substrate containing an access hole. For some applications one or multiple layers of protective coatings can be deposited on either one side or both sides of the sensor package for protection against the operating environment.

Abstract: An integrated circuit is described which includes a metal level primarily comprising probe pads for testing the integrated circuit. This additional metal level is isolated from the integrated circuit upper metal level by an insulating layer. This probe metal level is selectively connected to the metal level and other regions of the integrated circuit to form electrical connections. The probe metal level allows for accurate and extensive pre-production testing of the integrated circuit without sacrificing valuable real-estate of the metal level. The probe metal level and the insulating layer are described as useful during pre-production phases and are preferably eliminated during production of the integrated circuit.

Abstract: To enable readily forming the etching stop layer of a lead frame with multilayer structure by plating without using a large-scale device, enhance adhesive strength between the etching stop layer and an adjacent metal layer and prevent peeling caused by deterioration caused by the invasion of a chemical between the etching stop layer and each adjacent metal layer from occurring, an etching stop layer is formed by nickel or a nickel alloy in a method of manufacturing a lead frame at least provided with an etching process for selectively etching metal layers using an etching stop layer as an etching stopper in a state in which a thick metal layer is formed on one side of the etching stop layer as an intermediate layer and a thin metal layer is formed on the other side and a process for etching the etching stop layer using the metal layers on both sides as a mask.

Abstract: In an active area surrounded with an isolation formed on a silicon substrate, a large number of unit cells are disposed in a matrix, and the unit cell together form one MOSFET. Each of the unit includes a ring gate electrode in the shape of a regular octagon, a drain region and a source region formed at the inside and outside of the gate electrode, respectively, two gate withdrawn wires extending from the gate electrode to area above the isolation, a substrate contact portion in which the surface of the substrate is exposed, and contacts for electrically connecting these elements with wires. These elements such as the ring gate electrode and the gate withdrawn wires are formed so as to attain a high frequency characteristic as good as possible. Thus a MOSFET for use in a high frequency signal device, the high frequency characteristic such as the minimum noise figure and the maximum oscillation frequency in particular can be totally improved.

Abstract: An integrated circuit is provided. The integrated circuit includes a substrate and at least one dielectric layer and a metal layer formed upon the substrate. The at least one dielectric layer includes a terminal dielectric layer. The integrated circuit further includes a planar passivating layer formed upon the terminal dielectric layer.

Abstract: A thin, stacked face-to-face integrated circuit packaging structure includes a chips attached to both major surfaces of a rigid interposer, and interconnected by printed wiring traces and vias to external solder ball contacts attached to the interposer.

Abstract: There is provided a method of fabricating a CMOS semiconductor device including nMOSFET and pMOSFET, including the steps of (a) forming a gate insulating film on a semiconductor substrate, (b) forming a first polysilicon film on the gate insulating film, (c) forming an interlayer insulating film on the first polysilicon film, (d) forming a second polysilicon film on the interlayer insulating film, (e) shaping the first polysilicon film, the interlayer insulating film, and the second polysilicon film into a gate electrode in both a first region where the nMOSFET is to be fabricated and a second region where the pMOSFET is to be fabricated, and (f) doping n-type impurities into the first region and p-type impurities into the second region by ion-implantation. The method makes it possible to prevent reduction in dielectric voltage of a gate insulating film, which would be caused by diffusion of titanium atoms, without causing a gate electrode to be depleted.

Abstract: An electronic component includes an inner lead having a tip with a projection; an insulating coating that is electrically conductive when heated disposed around the projection; and a metallic coating disposed around an electrode on a semiconductor chip, with a crater reaching the electrode, the projection engaging the crater to make a contact between the inner lead and the electrode, the insulating coating and the metallic coating being anodically bonded to each other.

Abstract: Heterostructure field-effect transistors (HFETs) and other electronic devs are fabricated from a series of semiconductor layers to have reduced impact ionization. On to a first barrier layer there is added a unique second subchannel layer having high quality transport properties for reducing impact ionization. A third barrier layer having a controlled thickness to permit electrons to tunnel through the layer to the subchannel layer is added as a spacer for the fourth main channel layer. A fifth multilayer composite barrier layer is added which has at least a barrier layer in contact with the fourth channel layer and on top a sixth cap layer is applied. The device is completed by adding two ohmic contacts in a spaced apart relationship on the sixth cap layer with a Schottky gate between them which is formed in contact with the fifth barrier layer.

Abstract: A semiconductor device comprises a semiconductor chip having a major surface, a plurality of bonding pads provided on the major surface of the semiconductor chip, an adhesive tape provided on a selected part of the major surface of the semiconductor chip, and a plurality of inner leads mounted on the adhesive tape, each adhered at a lower surface thereof to the adhesive tape. The device further comprises a wiring lead, bonding wires, and a resin-molded package. The wiring lead has at least one end portion and spaced apart from the major surface of the chip. The at least one end portion is depressed from the inner leads toward the semiconductor chip, located outside the adhesive tape and formed integral with at least one of the inner leads.

Abstract: A semiconductor package is disclosed. According to one embodiment, the package comprises a substrate having a top surface with traces thereon and a bottom surface with solder balls thereon, the substrate comprising at least three material layers defining at least four substantially planar metal layers, wherein one of the metal layers comprises a reference layer that serves as a reference to both traces on a metal layer above the reference layer and traces on a metal layer below the reference layer. A semiconductor die is mounted to the substrate and bonding wires electrically connect the semiconductor die to the traces on the top surface of the substrate. The traces on the top surface of the substrate are electrically connect to the solder balls through vias and possibly through routing on another metal layer.

Abstract: On an n-type semiconductor substrate 41 doped in high density, a p-type semiconductor layer 2, an n-type semiconductor layer 4 doped in high density, which is a collector, a p-type semiconductor layer 6 doped in high density, which is a base, and the n-type semiconductor layer 7, which is an emitter, are sequentially stacked. To the collector layer, a collector electrode 12 is electrically connected, and to the base layer, a base electrode 11 is electrically connected, and to the emitter layer, an emitter electrode 9 is electrically connected, and thus a bipolar transistor is structured. On the bipolar transistor, an insulated isolation area 55 is formed with an opening therein, whose depth reaches the surface of the substrate, and a substrate electrode 48 is formed thereon. On the bipolar transistor and the insulated isolation area 55, an inter-layer dielectric layer 54 is formed having contact holes formed to upper parts of the emitter electrode 49 and to the substrate electrode 48.

Abstract: An interlayer insulating film of a semiconductor device is made of a material in which silicon atoms are main elements, and each of the silicon atoms has an oxygen bond and a carbon bond, and further at least some of the silicon atoms have a hydrogen bond. The interlayer insulating film is formed by chemical vapor deposition employing a mixed gas of hydrogen peroxide and a reactive gas having a gas molecular structure in which silicon atoms have a hydrogen bond and a carbon bond.