Abstract: An epitaxial layer is formed on a main surface of a high specific resistance silicon substrate having a specific resistance of at least 100 .OMEGA.cm. A circuit element such as an active element is formed in epitaxial layer. An oxide film is formed such that it covers a surface of epitaxial layer. A metal interconnection layer is formed on a surface of oxide film. An oxide film is formed such that it covers metal interconnection layer. Thus, an inexpensive HF circuit device capable of reducing transmission loss of HF signals can be obtained.

Abstract: A stacked chip assembly generally includes a first chip, a second chip and a lead frame. The lower surface of the first chip is pasted onto the lower surface of the second chip by an adhesive film so as to form a stacked chip body. The stacked chip body is disposed on the lead frame. Bonding pads of the upper surface of the first chip are interconnected to the upper surface of the inner leads of the lead frame by bonding wires. Bonding pads of the upper surface of the second chip are interconnected to the lower surface of the inner leads of the lead frame by bonding wires. Therefore, the first chip and the second chip are simultaneously interconnected to an external circuit devices through the lead frame.

Abstract: The present invention discloses a semiconductor device which can be used as a switching element for portable appliances and realize a low breakdown voltage and a low ON resistance. More specifically, the semiconductor device is constructed in such a manner that a semiconductor layer is vertically or laterally sandwiched between gate electrodes through insulation films. In this polycrystalline semiconductor layer, a source region and a drain region are formed in both end portions thereof which contain an impurity at a concentration higher than the concentration in the middle portion thereof, and, in the middle portion, a channel region is formed, whereby carriers can be made to flow throughout the whole channel region.

Abstract: A semiconductor device comprises a high-resistance n type base layer, an n type drain layer formed on one surface of the n type base layer, p type base layers selectively formed at the other surface of the n type base layer, n type source layers selectively formed at surfaces of the p type base layers, p type injection layers selectively formed at the other surface of the n type base layer in regions different from regions where the n type source layers and p type base layers are formed, a trench selectively formed to extend from a surface of each n type source layer through the p type base layer into the n type base layer, a first gate electrode buried in the trench with an insulating film interposed, a drain electrode formed on the n type drain layer, a source electrode formed on the n type source layer, and a second gate electrode formed on the p type injection layer.

Abstract: A semiconductor package includes a stiffener strip (10) having a die pad (18) and a body portion (12). A first surface (4) of the die pad (18) is offset from a second surface (3) of the body portion (12) a predetermined amount. The stiffener strip (10) includes an internal edge (27) concentrically disposed about the die pad (18) and tie straps (16) connecting the internal edge (27) to the die pad (18). A die (28) is affixed to the first surface (4) of the die pad (18). A substrate (20) has a first surface (17) and a second surface (19), with the second surface (19) being affixed to the first surface (2) of the body portion (12). The substrate (20) includes a window (22) and conductive elements (24). A plastic molding material (33) encompasses the die (28), at least a portion of the stiffener strip (10), and at least a portion of the substrate (20).

Abstract: The invention is a process for reducing roughness of a surface of a superconductor material (23) having an undesirable surface roughness (30 and 32) and a trilayer superconductor integrated circuit (100). The process for reducing roughness of a surface of superconductor material having an undesirable surface roughness includes coating the surface with an oxide layer (40) to fill the undesirable surface roughness and to produce an exposed oxide surface (42) with a roughness less than the surface roughness; and etching the exposed oxide surface to remove a thickness of the oxide layer followed by removing at least a portion of the oxide layer filling the undesirable surface roughness and a portion of the surface of the superconductor material to produce an exposed etched surface (44) comprised of at least the superconductor material which has a surface roughness less than the undesirable surface roughness.

Abstract: A gallium nitride group compound semiconductor light-emitting device comprises a substrate and a layered structure provided on the substrate. The layered structure includes: an active layer; an upper cladding layer and a lower cladding layer which is located closer to the substrate than the upper cladding layer, the active layer interposed between the cladding layers; an internal current constricting layer having an opening for constricting a current within a selected region of the active layer, the internal current constricting layer being provided on the upper cladding layer; a surface protecting layer for covering the internal current constricting layer and an exposed surface of the upper cladding layer in the opening of the internal current constricting layer; and a regrowth layer provided on the surface protecting layer. The surface protecting layer serves as a protecting layer for the upper cladding layer and the internal current constricting layer in a step of forming the regrowth layer.

Abstract: A first metal film and a second metal film, both of which are made of Ni or the like, are deposited on the upper surface of a substrate made of SiC. In such a state, the interface between the first metal film and the substrate and the interface between the second metal film and the substrate both form a Schottky contact. Next, laser light is irradiated from above the upper surface of the substrate only onto the first metal film on the substrate after the diameter of the top end of the laser light has been reduced. Thus, since the metal-semiconductor interface between the first metal film and the substrate is turned into an alloy owing to the energy of the laser light without heating the entire substrate, an ohmic contact can be formed in the interface between the first metal film and the substrate. As a result, an ohmic electrode can be constituted by the first metal film.

Abstract: Impurity regions shaped in linear patterns are formed in parallel with the channel direction (electric field direction) in a channel forming region. The impurity regions restrain the expansion of the drain side depletion layer, and the narrow channel effect is exhibited to prevent the short channel effect. Also, in the channel forming region, the impurity regions control the carrier moving directing in one way, to thereby restrain the scattering caused by irregular collision between the carriers.

Abstract: An object of the invention is to provide a light emitting diode which enables relatively easy fabrication of large-area displays and is applicable to thin, long life, low cost, full color displays too. The object is attained by a light emitting diode comprising a positive electrode, a negative electrode, an inorganic light emitting layer between the electrodes exhibiting at least electroluminescence, an inorganic electron transporting layer between the inorganic light emitting layer and the negative electrode comprising as a main component at least one oxide selected from among strontium oxide, magnesium oxide, calcium oxide, lithium oxide, rubidium oxide, potassium oxide, sodium oxide, and cesium oxide, and an inorganic hole transporting layer between the inorganic light emitting layer and the positive electrode, the inorganic hole transporting layer being an inorganic insulative hole transporting layer comprising an oxide of silicon and/or germanium as a main component.

Abstract: A method for fabricating an array of ultra-small pores for use in chalcogenide memory cells. A layer of a first material is applied onto a substrate. A portion of the layer of the first material is then removed to define an upper surface with vertical surfaces extending therefrom to a lower surface in the first layer of the first material. A fixed layer of a second material is then applied onto the vertical surfaces of the first layer of the first material. The fixed layer of the second material has a first thickness. A second layer of the first material is then applied onto the fixed layer of the second material. The fixed layer of the second material is then removed to define an array of pores in the first material layers. The pores thus defined have minimum lateral dimensions ranging from approximately 50 to 500 Angstroms and cross sectional areas greater than or equal to the first thickness of the second layer squared.

Abstract: An improved circuit and method for gate-body transistors is provided. The improved circuit and method can accord a faster switching speed and low power consumption. The present invention capitalizes on opposing sidewalls and adjacent conductive sidewall members to conserve available surface space on the semiconductor chips. The gate and body of the transistors are biased to modify the threshold voltage of the transistor (V.sub.t). Additionally, the conductive sidewall members and a gate are biased from a single source. The structure offers performance advantages from both metal-oxide semiconductor (MOS) and bipolar junction transistor (BJT) designs. The device can be used in a variety of applications, digital and analog, wherever a more compact structure with low power consumption and fast response time is needed.

Abstract: A recess is made in the semiconductor substrate. A gate electrode has a sectional shape of "T" to have a head overhanging portion and is made in the recess. The gate electrode having a head overhanging portion. A capacitance film is formed under the head overhanging portion of the gate electrode. An ohmic electrode is formed on the semiconductor substrate and at both sides of the gate electrode. In the device, the capacitance film is made of a photosensitive organic film having a smaller permittivity than that of silicon oxide films. This semiconductor device has a small gate parasitic capacitance and the variation in the capacitance can be reduced.

Abstract: A semiconductor device includes a semi-insulating substrate. A channel layer is formed on the semi-insulating substrate. An electron supply layer is formed on the semi-insulating substrate for generating a two-dimensional electron gas. The electron supply layer includes a doped superlattice layer. The superlattice layer includes layers of In.sub.X Al.sub.1-X As and layers of In.sub.Y Al.sub.1-Y As which alternate with each other, where 0.ltoreq.X.ltoreq.1.0 and 0.ltoreq.Y.ltoreq.1.0, and X differs from Y.

Abstract: A semiconductor device is provided wherein carrier flows in a monocrystal silicon film having low oxygen concentration. As for a structure of the semiconductor device, a single semiconductor element or a plurality of semiconductor elements are provided on the monocrystal silicon film having low oxygen concentration which is provided on a backing substrate of which at least the surface is made of an insulating material. The backing substrate is provided so that the semiconductor device gets mechanical destructive strength. The insulating material is provided so that some particles never transfers from the backing substrate to the semiconductor film. The silicon film has-low oxygen concentration so that the lifetime of a minor carrier lengthens.

Abstract: A semiconductor device has a drift region in which a drift current flows if it is in the ON mode and which is depleted if it is in the OFF mode. The drift region is formed as a structure having a plurality of first conductive type divided drift regions and a plurality of second conductive type compartment regions in which each of the compartment regions is positioned among the adjacent drift regions in parallel to make p-n junctions, respectively.

Abstract: A semiconductor logic element is provided which is capable of a plurality of logic operations. The semiconductor logic element includes a semiconductor substrate on which is disposed at least three control electrodes and an output electrode for outputting signals in response to inputs to said control electrodes, making it possible to significantly reduce the number of elements constituting a logic circuit and to provide high speed processors and electronic computers. Logic circuitry and apparatus using the semiconductor logic elements are also provided.

Abstract: A semiconductor integrated circuit, a supply method of supplying multiple supply voltages therefor, and a record medium for storing a program of the supply method for supplying multiple voltages therefore in which a first cell to which multiple supply voltages are supplied is extracted (Step S1), the extracted cells are divided into groups (Step S2), cells for voltage supply are added and arranged according to the number of the groups (Step S3), and the cell for the voltage supply are connected to the first cell for supplying the plurality of voltages through a net for a power source supply (Step S4).

Abstract: The invention provides a semiconductor device, having a variety of functions such as a bistable memory and a logic circuit, in which a MOS semiconductor element, a resonance tunnel diode, a hot electron transistor and the like are formed on a common substrate. An n-type Si layer and a p-type Si layer surrounded with an isolation oxide film are formed on an SOI substrate. A mask oxide film and a gate oxide film are formed, and the n-type Si layer is subjected to crystal anisotropic etching by using the mask oxide film as a mask, so as to change the n-type Si layer into the shape of a thin Si plate. After first and second tunnel oxide films are formed on side faces of this n-type Si layer, first and second polysilicon electrodes of a resonance tunnel diode and a polysilicon electrode working as a gate electrode of a MOS semiconductor element are formed out of a common polysilicon film. Thus, a Si/SiO.sub.2 type quantum device can be manufactured with ease at a low cost.

Abstract: In accordance with the present invention, there is provided an electrically insulating substrate having first and second surfaces, an outline and an opening. A plurality of electrically conductive routing strips is integral with the substrate. A plurality of contact pads is disposed on the first surface, at least one of the pads being electrically connected with at least one of the routing strips. A semiconductor chip is adhered to the second surface of the substrate. The chip has an outline that is substantially the same as the outline of the substrate. The chip has at least one bonding pad. Wire bonding electrically connects the bonding pad to a routing strip.At least one bus bar is integral with the substrate. The bus bar is positioned remote from the substrate opening and is electrically connected to a bonding pad of the chip and to a contact pad disposed on the first surface of the substrate.