Abstract: A physical unclonable functions (PUF) device including a first copper electrode, a second electrode, and a silicon oxide layer positioned directly between the first copper electrode and the second electrode; a method of producing a PUF device; an array comprising a PUF device; and a method of generating a secure key with a plurality of PUF devices.

Abstract: The present disclosure relates an integrated chip. The integrated chip includes a semiconductor device arranged along a first side of a semiconductor substrate. The semiconductor substrate has one or more sidewalls extending from the first side of the semiconductor substrate to an opposing second side of the semiconductor substrate. A dielectric liner lines the one or more sidewalls of the semiconductor substrate. A through-substrate-via (TSV) is arranged between the one or more sidewalls and is separated from the semiconductor substrate by the dielectric liner. The TSV has a first width at a first distance from the second side and a second width at a second distance from the second side. The first width is smaller than the second width and the first distance is smaller than the second distance.

Abstract: The disclosed technology provides micro-assembled micro-LED displays and lighting elements using arrays of micro-LEDs that are too small (e.g., micro-LEDs with a width or diameter of 10 ?m to 50 ?m), numerous, or fragile to assemble by conventional means. The disclosed technology provides for micro-LED displays and lighting elements assembled using micro-transfer printing technology. The micro-LEDs can be prepared on a native substrate and printed to a display substrate (e.g., plastic, metal, glass, or other materials), thereby obviating the manufacture of the micro-LEDs on the display substrate. In certain embodiments, the display substrate is transparent and/or flexible.

Abstract: A semiconductor device includes a substrate, a bottom etch stop layer over the substrate, a middle etch stop layer over the bottom etch stop layer, and a top etch stop layer over the middle etch stop layer. The top, middle, and bottom etch stop layers include different material compositions from each other. The semiconductor device further includes a dielectric layer over the top etch stop layer and a via extending through the dielectric layer and the top, middle, and bottom etch stop layers. The via has a first sidewall in contact with the dielectric layer and slanted inwardly from top to bottom towards a center of the via and a second sidewall in contact with the bottom etch stop layer and slanted outwardly from top to bottom away from the center of the via.

Abstract: One aspect of this description relates to an integrated circuit. In some aspects, the integrated circuit includes a first pattern metal layer, a second pattern metal layer disposed over the first pattern metal layer, wherein the second pattern metal layer includes a second plurality of metal tracks extending in a first direction, and a third pattern metal layer disposed between the first pattern metal layer and the second pattern metal layer, the third pattern metal layer including a first metal track segment and a second metal track segment shifted in a second direction from the first metal track segment, wherein the second plurality of metal tracks, and at least a portion of each of the first metal track segment and the second metal track segment are within a double cell height in the second direction.

Abstract: A semiconductor memory device comprising: a first semiconductor chip including an upper input/output pad, a second semiconductor chip including a lower input/output pad, and a substrate attachment film attaching the first and second semiconductor chips. The first and second semiconductor chips each include a first substrate including a first side facing the substrate attachment film and a second side, a mold structure including gate electrodes, a channel structure penetrating the mold structure and intersecting the gate electrodes, a second substrate including a third side facing the first side and a fourth side, a first circuit element on the third side of the second substrate, and a contact via penetrating the first substrate and connected to the first circuit element. The upper and lower input/output pads are on the second sides of the first and second semiconductor chip, respectively, and contact the contact vias of the first and second semiconductor chips.

Abstract: In a method for forming a semiconductor device, a channel structure is formed that extends from a side of a substrate, where the channel structure includes sidewalls and a bottom region. The channel structure further includes a bottom channel contact that is positioned at the bottom region and a channel layer that is formed along the sidewalls and over the bottom channel contact. A high-k layer is formed over the channel layer along the sidewalls of the channel structure and over the bottom channel contact.

Abstract: Methods, systems, and devices for reduced resistivity for access lines in a memory array are described. A first metal layer may be formed above a via that is configured to couple an access line of a memory array with a corresponding driver. The first metal layer may be oxidized, and then a second metal layer may be formed above the oxidized first metal layer. One or more access lines of the memory device may be formed from the second metal layer, the oxidized first metal layer, or both.

Abstract: A thin-film resistor (TFR) module is formed in an integrated circuit device. The TFR module includes a pair of metal TFR heads (e.g., copper damascene trench structures), a TFR element formed directly on the metal TFR heads to define a conductive path between the pair of TFR heads through the TFR element, and TFR contacts connected to the TFR heads. The TFR heads may be formed in a metal interconnect layer, along with various interconnect elements of the integrated circuit device. The TFR element may be formed by depositing and patterning a TFR element/diffusion barrier layer over the TFR heads and interconnect elements formed in the metal interconnect layer. The TFR element may be formed from a material that also provides a barrier against metal diffusion (e.g., copper diffusion) from each metal TFR head and interconnect element. For example, the TFR element may be formed from tantalum nitride (TaN).

Abstract: A method for fabricating semiconductor device includes the steps of: forming a dielectric layer on a substrate; forming a trench in the dielectric layer; forming a first liner in the trench, wherein the first liner comprises Co—Ru alloy; forming a metal layer on the first liner; and planarizing the metal layer and the first liner to form a metal interconnection.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate, a semiconductor fin and a filled trench. The semiconductor fin extends upwards from the semiconductor substrate. The filled trench is formed in the semiconductor fin and includes a first sigma portion, a second sigma portion and a middle portion. The first sigma portion is partially filled by a semiconductor buffer region, and an unfilled part of the first sigma portion is filled by a doped semiconductor region grown on the semiconductor buffer region. The second sigma portion is filled by the semiconductor buffer region. The middle portion connects the first sigma portion to the second sigma portion, and the middle portion is filled by the semiconductor buffer region.

Abstract: A semiconductor structure and a method for forming the same are disclosed. The method includes the steps of forming a first dielectric layer on a substrate, forming a plurality of first interconnecting structures in the first dielectric layer, forming at least a trench in the first dielectric layer and between the first interconnecting structures, performing a sputtering deposition process to form a second dielectric layer on the first dielectric layer, wherein the second dielectric layer at least partially seals an air gap in the trench, and forming a third dielectric layer on the second dielectric layer.

Abstract: A semiconductor device may include a substrate including a first surface and a second surface, which are opposite to each other, an insulating layer on the first surface of the substrate, a first via structure and a second via structure penetrating the substrate and a portion of the insulating layer and having different widths from each other in a direction parallel to the first surface of the substrate, metal lines provided in the insulating layer, and an integrated circuit provided on the first surface of the substrate. A bottom surface of the first via structure may be located at a level lower than a bottom surface of the second via structure, when measured from the first surface of the substrate. The second via structure may be electrically connected to the integrated circuit through the metal lines.

Abstract: A semiconductor device includes a conductive pattern formed over a semiconductor substrate, and an interconnect structure formed over the conductive pattern. The semiconductor device also includes a first passivation layer over the conductive pattern; a second passivation layer over the first passivation layer; an interconnect structure disposed over the conductive pattern and in the first passivation layer and the second passivation layer; and an interconnect liner disposed between the interconnect structure and the conductive pattern and surrounding the interconnect structure, wherein inner sidewall surfaces of the interconnect liner are in direct contact with the interconnect structure, and a maximum distance between outer sidewall surfaces of the interconnect liner is greater than a width of the conductive pattern.

Abstract: A method of forming an acoustic transducer comprises providing a substrate and depositing a first structural layer on the substrate. The first structural layer is selectively etched to form at least one of an enclosed trench or an enclosed pillar thereon. A second structural layer is deposited on the first structural layer and includes a depression or a bump corresponding to the enclosed trench or pillar, respectively. At least the second structural layer is heated to a temperature above a glass transition temperature of the second structural layer causing the second structural layer to reflow. A diaphragm layer is deposited on the second structural layer such that the diaphragm layer includes at least one of a downward facing corrugation corresponding to the depression or an upward facing corrugation corresponding to the bump. The diaphragm layer is released, thereby forming a diaphragm suspended over the substrate.

Abstract: Devices, systems, and methods for forming twisted conductive lines are described herein. One method includes: forming a first row and a second row of a first number of vertical conductive line contacts, the vertical contacts in each row are arrayed in a first horizontal direction and the first row is spaced from the second row in a second horizontal direction; forming a number of conductive lines with curved portions, each conductive line making contact with alternating conductive line contacts of the first and second rows of the first number of vertical conductive line contacts; and forming a second number of conductive lines with one or more curved portions, each conductive line making contact with the remaining ones of the conductive line contacts of the first and second rows of the first number of vertical conductive line contacts that have not been contacted by the first number of conductive lines.

Abstract: A cross-couple contact structure is provided that is located on, and physically contacts, a topmost surface of a functional gate structure that is located laterally adjacent to a gate cut region. The cross-couple contact structure extends into the laterally adjacent gate cut region and physically contacts a sidewall of the functional gate structure, an upper portion of a first sidewall of a dielectric plug that is present in the gate cut region, and an upper surface of a dielectric liner that is located on a lower portion of the first sidewall of the dielectric plug.

Abstract: The present application discloses a semiconductor device with a carbon hard mask. The semiconductor device includes a substrate, conductive layers positioned on the substrate, a carbon hard mask layer positioned on the conductive layers, an insulating layer including a lower portion and an upper portion, and a conductive via positioned along the upper portion of the insulating layer and the carbon hard mask layer and positioned on one of the adjacent pair of the conductive layers. The lower portion is positioned along the carbon hard mask layer and positioned between an adjacent pair of the conductive layers, and the upper portion is positioned on the lower portion and on the carbon hard mask layer.

Abstract: A semiconductor device and related manufacturing methods are provided. The semiconductor device includes one interconnection structure including: a substrate; a first insulating dielectric layer underneath a lower surface of the substrate; a second insulating dielectric layer on an upper surface of the substrate; a first connecting pad disposed within the first insulating dielectric layer; a metal connection member penetrating through a portion of the second insulating dielectric layer, the substrate and a portion of the first insulating dielectric layer to connect the first connecting pad; and a second connecting pad disposed within the second insulating dielectric layer and connecting the metal connection member. The metal connection member may be a Through-Silicon Via (TSV). The device includes a confined air gap surrounding the metal connection member, which improves the performance and reliability of the device.

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a conductive structure arranged within a substrate or a first dielectric layer. A first barrier layer is arranged on outermost sidewalls and a bottom surface of the conductive structure. A second barrier layer is arranged on outer surfaces of the first barrier layer. The second barrier layer separates the first barrier layer from the substrate or the first dielectric layer. A second dielectric layer is arranged over the substrate or the first dielectric layer. A via structure extends through the second dielectric layer, is arranged directly over topmost surfaces of the first and second barrier layers, and is electrically coupled to the conductive structure through the first and second barrier layers.