Abstract: A programmable multiphase clock divider for selectively frequency dividing a multiphase input clock to provide a lower-frequency, self-aligned, multiphase output clock includes a counter, combinational logic circuitry, a multiphase signal generator and a multiplexor. With the counter serving as the sole frequency divider element, multiple phase-aligned clock phases are generated which are then programmably multiplexed to provide the desired frequency-divided, self-aligned clock phases. The counter, in response to a preset signal and an input clock phase, generates a multibit count signal, one bit of which forms the first output clock phase. The combinational logic circuitry receives a programming signal for decoding the multibit count signal to generate the counter preset signal and an output control signal.

Abstract: A device for printing an image onto a surface, such as food containers, employs a laser that is scanned across a surface to produce a latent image on a charged photosensitive surface formed on the surface. The surface is moved relative to the laser source while the laser is activated and deactivated according to a pattern of signal pulses from a control circuit. The device thus forms a raster image. To form very fine images, the control circuit must produce pulses with very small steps in duration. The control circuit of the present invention divides a digital value representing a duration of firing of the laser into high and low order bit sequences. The high order bits, representing a value M, are applied to a counter that generates a first pulse M clock cycles long. The low order bits and the first pulse are applied to a delay circuit. The delay circuit generates a delayed version of the first pulse, which is delayed by an amount represented by the low order bits.

Abstract: An ultra low power gain circuit (UGC) implements a unique operational mode of a source follower circuit, and enables programmable gains greater than unity. A MOSFET has a gate terminal coupled to an input capacitance (Cin). A potential at a drain of the MOSFET is clocked to enable charge to flow through the channel. This charge charges a capacitor (Cout) that is connected to a source of the MOSFET. After charging Cout, the drain potential is restored to an initial value, and the charge on Cout discharges back through the MOSFET until the source voltage is one threshold drop from the gate potential, at which time the MOSFET turns off. Cout then stops discharging, and the final voltage appearing on Cout is a function of the magnitude of the gate voltage appearing on Cin. As the voltage at the source of the MOSFET changes, capacitive coupling, via (Cgs) to the gate, causes the gate voltage to also change. The value of the gate voltage determines a magnitude of a final voltage to which the source settles.

Abstract: A speedometer/odometer apparatus, wherein a sensor inputs an electronic sensing signal to an amplifier and a selecting device to be amplified and output as a stable single stroke signal. The signal is combined with a frequency signal from a crystal oscillator and divided into regular pulses. The frequency of the pulses is divided by a frequency divider circuit and output as two signals with high accuracy for respectively controlling the speed indication of the speedometer and mileage indication of the odometer.

Abstract: An electronic combined pulse meter and pedometer may be provided with only a single sensor used for determining walking pace and pulse rate. A pulse wave detector detects a pulse wave of the user and outputs a corresponding pulse wave signal to a calculating circuit and a walking state detector. The walking state detector compares the detected pulse wave with a reference level stored in a pulse wave level memory and outputs a walking state signal if the level of the detected pulse wave exceeds the reference level. Calculation control circuitry selects various constant values pre-stored in a constant value memory based upon the walking state signal and outputs the selected constant values to the calculating circuit and a display device. The calculating circuit calculates the time interval between successive pulses of the detected pulse wave signal in accordance with a clock signal and the selected constant values, and outputs the result to the display device.

Abstract: An N stage counter includes peripheral circuitry for testing the operability of the counter. The peripheral circuitry includes gating means coupled between certain stages of the counter for partitioning the counter into at least first and second counter sections during a testing mode. During the testing mode, the N counter stages are reset to an all zero condition and this resettability capability is detected. During the testing mode, the N counter stages are also set to a predetermined value and the settability of the counter stage to a non-zero condition is also detected. During one phase of the testing mode, the first section counts a predetermined number of clock cycles while all counts produced at the outputs of all the stages of the second section are totalled in a register means. During another phase of the testing mode, the second section counts a predetermined number of clock cycles while all the counts produced at the outputs of all the stages in the first section are totalled in the register means.

Abstract: Comparator circuitry and a method of operation are provided. First and second match lines are precharged. First and second information are compared, and the first match line is selectively discharged in response thereto. Third and fourth information are compared, and the second match line is selectively discharged in response thereto. The second match line is discharged in response to discharging the first match line.

Abstract: A drive circuit comprises a plurality of current mirrors connected in series at their output-current end with a load resistor between two power rails. The input halves of the mirrors are driven by respective groups of series-connected input transistors, the lowest transistor in each group serving to set up the required currents in the mirrors in response to an input voltage on its base. Two potential dividers set up potentials on the control terminals of the groups of input transistors, on the one hand, and potentials on the main-terminal junctions of the mirror output transistors, on the other, such that at no time does any transistor in the circuit experience a voltage greater than its rated voltage.

Abstract: A drive circuit for use in UPS and like devices, designed to derive high-level switching signals from low-level logic signals. The drive circuit has an input circuit which drives the primary of an air-core transformer, the input drive circuit having an oscillator with a resonant circuit producing a carrier at a carrier frequency, the resonant circuit including the primary of the transformer and a coupling circuit for coupling the logic signals to the oscillator so as to modulate the carrier signal. The use of the resonant circuit enables generation of sufficient magnetization current for the low-cost transformer while reducing the current drive required of the input drive circuit, thereby enabling a reduced cost gate drive circuit.

Abstract: A frequency divider, constituted by N divide-by-two binaries, comprises logic circuits that enable the generation of a signal of the end of the frequency division by means of the change in state of the most significant bit generated by the Nth order divide-by-two binary. A binary code C representing a decimal integer value V is applied to the divider circuit. The frequency divider comprises circuits that enable the performance of a variable order division (V+1, V, . . . V-p, where p is a whole number greater than or equal to 1 and smaller than N-1) for one and the same binary code C.

Abstract: A spline counting mechanism for determining the number of splines on a shaft. The spline counting mechanism includes a plunger urged into engagement with the shaft and adapted to be rotated with respect to the shaft. The plunger is adapted to engage each spline on the shaft as the plunger is rotated through one revolution and is operable to establish and cut off electrical continuity in an electrical circuit as the plunger rotates into engagement with and then beyond each spline. The mechanism further includes a digital counter for counting and displaying the number of times that electrical continuity is established in the electrical circuit, this number being equal to the number of splines on the shaft.

Abstract: A timer has a function of compensation calculation and includes a compensation value register 1 for holding a compensation value and an arithmetic unit 2 which adds or subtracts a compensation value ".alpha." held in the compensation value register 1 and a value "CC" of a count value C of a counter 3 at that time point, and by loading the operation result of the arithmetic unit 2 to the counter 3. Such a timer reduces a burden on a CPU and is capable of compensating the count value correctly regardless of a remaining time.

Abstract: A counter circuit converts a full count to a zero count and a zero count to a full count. An incrementing counter circuit according to the present invention has a plurality of threshold circuits with stepwise thresholds. An output of the highest threshold circuit is used as a cut off signal for other threshold circuits. A decrementing counter circuit according to the present invention has a plurality of threshold circuits from the lowest threshold to the highest thresholds. An output of the lowest threshold circuit is used as a closing signal for other threshold circuits.

Abstract: A general object of the present invention is to provide a latch of which demand is small. In a half-latch 101, control signals T2 and T2C which vary at late timings are applied to a main unit for data input (update) operation while control signals T1 and T1C which vary at early timings are applied to a feedback unit for data retaining operation. The data input (update) operation is never started until the data retaining operation is completed. The data retaining operation is practiced by retaining two signals having a negative logic relation with each other in a loop made up with two inverters. A signal related to retension of data and a signal newly input never reside in the same signal line. Thus, collision of those signals is avoided, and consequently, through-current due to the collision of the signals can be reduced.

Abstract: A signal reproducing apparatus reproduces a signal recorded in a DAT by using a start ID. The signal reproducing apparatus includes an output circuit for reading out a signal from the DAT and for outputting a reproduction signal, a memory for storing signals, a controller for storing the reproduction signal from a predetermined region on the DAT by the output circuit, the predetermined region including a position identified by the start ID, a leading edge detector for detecting a position, in the memory, of a leading edge of the reproduction signal to be stored in the memory, a memory controller for reading out the reproduction signal starting from the position, in the memory, detected by the leading edge detector.

Abstract: The present invention provides an output level control circuit for a transmitter of an automobile telephone system which can output a transmission output signal of an output level indicated by a level setting signal with a high degree of accuracy. First and second level control circuits function for a low-level side and a high-level side, respectively, of the detection output of a detection circuit and perform weighting such that the outputs vary with linearity relative to the output signal of the amplifier. A control signal generation circuit causes a selection circuit to select a first or second error signal of a first or second comparison circuit, respectively. The first and second comparison circuits receive the output of the first or second level control circuit, respectively, and these control circuits process the detection output corresponding to the output level of the output signal of the amplifier indicated by a level setting signal.

Abstract: A Q-switching drive circuit utilizing a magnetization curve characteristic of a saturation reactor, thereby capable of achieving a semipermanent use life, a rapid switching into a Q-switching opening phase voltage, a maintenance of the Q-switching opening phase voltage for a period of several hundreds nanoseconds. The Q-switching drive circuit can operate at a high repeat rate. An initial closing phase-delayed voltage is maintained in the Q-switching drive circuit so that a prelasing phenomenon is prevented from occurring upon oscillating the laser. The Q-switching drive circuit utilizes a magnetization curve characteristic of the saturation reactor so that a characteristic of a rapid return of the phase voltage from the opening state to the closing state can be obtained.

Abstract: In a magnetic layer storage having a magnetic head positionable relative to a storage medium, a reference storage medium produced with high precision is employed for the individual calibration of the storage tape drive, and particularly a positioner means thereof. This reference storage medium carries a track pattern adapted to the respective application and whose exact position is known. During the test run of each and every individual tape drive, this reference storage medium is read, and the read signals are evaluated in order to identify offset of actual position of the magnetic head from its absolute position defined by the reference storage medium. Individual correction factors can be acquired from the relationship of the absolute position to the actual position, these correction factors being stored in the control electronics and being employed during normal operation for correcting the tolerances of the positioner means or of the magnetic head itself.

Abstract: A clocked comparator circuit compares the primary and backup power supply voltages to a system. When the primary voltage falls a given amount below the backup, the circuit provides a signal that may be used to switch to the backup power supply. When the primary voltage is again present, the circuit can switch back to primary power. Alternatively, or additionally, a signal may be generated to initiate graceful shutdown of the system. The clock to the comparator typically operates at a higher frequency when operating on the primary voltage, and a lower frequency when operating on the backup voltage. This circuit is typically used with a portable system that uses a rechargeable battery as its primary power supply. The backup power supply may be a long-life battery that provides power to only a portion of the system. For example, in a computer, only a static memory may be powered by the backup, to allow the full system to retain its proper configuration when the primary power supply is again activated.

Abstract: A ring counter includes a plurality of latches forming a shift register. A single bit is sequentially clocked through the shift register, so that only one output is active at any time. A logic circuit is connected to the outputs, and monitors the number of outputs which are active. If more than one output should somehow become active at one time, such as during power up, a reset signal is immediately generated to reset a single bit of the counter active. An external reset signal can also be applied to the logic circuit to force a reset of the counter.