Abstract: A programmable time-intervals generator comprising first and second digital counters, a memory, a digital divider and a digital adder. On the occurrence of a first event, the first counter starts counting, and on the occurrence of a second event, only the most significant bits of the number counted up to then are stored, thereby providing a division by truncation. From the stored number, at least two discrete fractions are obtained by the divider, whereafter said fractions are summed at the adder which operates on strings of bits. The second counter counts down the sum number and, on becoming cleared, generates a signal.

Abstract: An elapsed time recording device includes a counter (130) for incrementally advancing a count value from an initial value towards and beyond a threshold in response to successive clock pulses of a clock signal. Control logic (140) enables the counter (130) to incrementally advance the count value in response to a first input (pin 3) and a second input (pin 1) being at or near a first voltage level, and holds the count value in response to the first input (pin 3) being at or near a second voltage level and the second input (pin 1) being at or near the first voltage level. Setting logic (210) sets the count value to a value beyond the threshold in response to the first input (pin 3) and the second input (pin 1) being at or near the second voltage level when the count value is between the initial value and the threshold.

Abstract: A circuit, responsive to the application of primary power, generates signals to establish the initial state of a logic circuit. Generated signals are interposed on the logic circuit's input signal line until initialization is complete. After initialization, the logic circuit's input signal line is recoupled for normal operation.

Abstract: A programmable clock divider in which a system reference clock signal is divided by a programmed integer value. A storage register stores a value equal to the desired divisor minus two. A stored value of zero results in a divide by two. The stored value is loaded into a compare register and a counter is implemented to count reference clock signals. The compare register value and the counter value are compared by a comparator logic circuit. When the two values are equal, a flip-flop is toggled to switch the prescale clock value output. The flip-flop control logic includes circuitry for ensuring that odd divides exhibit an output clock frequency having a 50/50 duty cycle by controlling the flip-flop toggle to coincide with system clock edges. The flip-flop control logic also controls the timing for loading and resetting the compare and counter logic, respectively.

Abstract: In a noise canceler, a pilot-canceling signal without noise is applied to the inverting input of a subtracter via a first MOS transistor. When a noise signal is present, a pilot signal and noise signal passing through a capacitor are applied to the inverting input port of the subtracter via a second MOS transistor to cancel the noise signal contained in the composite input signal. In the canceler, external noise may be digitally converted and the inverted noise thereof stored in a memory. When a noise signal detector detects the external noise, inverted data corresponding to the external noise is output from the memory. The detector enables an address generator to continuously generate addresses. The memory reads out inverted noise patterns which are converted into analog form and transmitted via a speaker, thereby canceling noises produced by various electrical and electronic appliances as well as nearby automobiles and aircraft.

Abstract: A circuit is disclosed for reducing the number of signal lines passing through a connector (205) comprised of a shift register coupled to a plurality of input data lines and half as many output data lines. When a load signal is received, the shift register latches the data from the input data lines and immediately transmits half of the data to the output data lines and through the connector. When the shift register receives a shift signal, the other half of the data is shifted onto the same output lines and pass through the connector to achieve a two-to-one multiplexing function.

Abstract: Reduction of input capacitance in an analog storage array is achieved by reducing the parasitic capacitance presented to an analog signal line. Each column of the analog storage array is coupled to the analog signal line by a separate coupling switch. The switches are activated so that no more than two columns are coupled to the analog signal line at any time, with the next column to be accessed being coupled to the analog signal line prior to access to that column, and the last column being decoupled from the analog signal line after the last cell in the column has been accessed. Further the analog signal line may provide two input ports so that alternate columns of the array are coupled to one port, and the other alternate columns are coupled to the other port so that two adjacent columns are coupled to separate ones of the two ports.

Abstract: Swimming goggles include an AM/FM radio assembly as well as a lap counter. The radio assembly includes earphones that also include foam for plugging the swimmer's ear to prevent water from entering that ear. The goggles also include plastic temple pieces that serve a dual function of securely supporting the goggles on the swimmer and supporting the radio and lap counter.

Abstract: Inventory monitoring apparatus capable of real-time counting of objects added to or subtracted from a location whose inventory is to be monitored. The apparatus includes structure for supporting a plurality of objects and a lever adapted to be contacted and displaced by movement of the objects to and from the supporting structure. Movement of the lever in one direction triggers a switch which generates a signal indicating that an object is being added to the support structure. Similarly, opposite movement of the lever triggers another switch which generates a signal indicating that an object is being removed from the support structure. A microprocessor receives and counts the signals generated by the switches to provide a real-time total of the quantity of objects borne by the supporting structure.

Abstract: A pulse generator has a presetting clock synchronous counter having a count enable terminal, the counter which counts up input data using a clock signal whose basic unit of time width corresponds to its one period. The output from said counter is decoded to produce a first state signal. A second state signal is produced from said clock signal and a count enable signal for said counter. An output pulse having a desired pulse width is obtained by calculating the logical product of said first and second state signals.

Abstract: Ultrasonic fuel gauging apparatus for a fuel tank having a plurality of ultrasonic fuel level sensors for sensing fuel levels at respective predetermined locations in a tank based on echo ranging; a memory means for storing sensor data; and a state device for interrogating each of the sensors by controlling the application of transmit pulses to each of the sensors and for receiving output signals corresponding to return echoes, the state device operating in response to a sequential state counter.

Abstract: A data coincidence detecting circuit including a register for receiving n-bit data, a counter for counting up until 2.sup.n to compare the n-bit data with it, a comparator for comparing the outputs of the register and the outputs of the counter, respectively to generate a coincidence detecting signal, a mask portion connected to the output of the comparator for masking the period from a time point when the n-bit data is input to a time point when the input of data ends, and a logic circuit for logically adding the output of the mask portion and the output of the comparator to output the result.

Abstract: The CMOS high-voltage sensor circuit has a voltage reference including, for example, of four N-channel MOS transistors; one pass-gate P-channel transistor; one current-mirror P-channel MOS transistor; and a conventional high-voltage sensor including, for example, of two P-channel MOS transistors and one N-channel MOS transistor. The sensor circuit of this invention generates a high-voltage signal at the output if the input voltage is greater than both the reference voltage plus two P-channel threshold voltages and the supply voltage Vcc plus two P-channel threshold voltages. The power-up or power-down sequence may be in any order without adversely affecting the operation of the circuit of this invention.

Abstract: An audio mixer circuit on an integrated circuit chip performs a calibration operation on power up which calibrates out most of the offset voltages of the operational amplifiers used in the mixer. The calibration logic includes a shared calibrate circuit which provides timing signals to each operational amplifier and its associated calibration circuitry. The calibration operation is performed by digitally controlling and changing the bias current into each of the operational amplifiers until the offset voltage is compensated. A class A flip-flop circuit is used in the digital counter of the calibration circuitry to drive a current digital-to-analog converter.

Abstract: A semiconductor integrated circuit device comprising a temperature sensor including an element having a PN junction, an inverter for receiving an output of the temperature sensor, and a controller for controlling supply of an electric energy to a group of MOS integrated circuit elements on the basis of an output of the inverter, wherein the supply of the electric energy to the group of MOS integrated circuit elements is controlled on the basis of the output of the temperature sensor to automatically prevent the breakdown of the internal circuit due to excessive temperature rise by the device itself.

Abstract: A semiconductor integrated circuit comprises a semiconductor chip, a power supply terminal provided on the semiconductor chip for receiving a voltage from an external power supply source, an internal circuit provided on the semiconductor chip, a power supply circuit provided on the semiconductor chip for transforming an external power supply voltage received from the power supply terminal for supplying a source voltage resulting from the voltage transformation to the internal circuit, and a control circuit provided on the semiconductor chip for controlling the power supply circuit, wherein the control circuit includes external power supply voltage detecting means and/or temperature detecting means and responds to the signal from the external power supply voltage detecting means and/or the temperature detecting means by changing the power supply voltage to the internal circuit to thereby maintain the operating speed of the internal circuit to be constant.

Abstract: A technique for generating gated clock signals for use in enabling various operating gating units in a data processing system in which an internal reference clock signal is used to generate both processor clock signals and the gated clock signals such that the latter signals are substantially synchronous with the processor clock signals. D-flip-flop circuitry together with a delay unit having an adjustable time delay are used to generate a gated clock signal. The overall time delay, from the time of which the circuitry is enabled until the gated clock signal is produced, is appropriately set by selecting the required time delay so that the overall time delay is essentially the same as the time delay required to generate the processor clock signals. Accordingly, the edges of the gated clock signals can be made to coincide with the edges of the processor clock signals.

Abstract: A high speed CMOS current switching circuit suitable for use in digital to analog converters for graphic interfaces having high pixel clock rates (high display resolutions), and such interfaces as may be used in portable and other battery operated or low power consumption applications. In operation, the current switching circuit normally steers an idle current to ground. If the bit of the digital to analog converter input digital signal represented by the respective source is a 1, the input signal representing the bit is delayed slightly while the current steered to ground is increased from the idle value to the full desired output current, whereupon at the end of the delay, the device coupling the output current to ground is turned off, thereby forcing the output current through an output device.

Abstract: An output circuit, having a plurality of bipolar transistors for driving a CMOS circuit, comprises an output level maintaining transistor connected between an output terminal of the output circuit and ground. The output level maintaining transistor maintains a level of the output terminal at a specific high potential by transmitting a current from the output terminal to the ground when the output circuit is outputting a high level signal to the output terminal, and the output level maintaining transistor is cut OFF when the output circuit is outputting a low level signal to the output terminal. Consequently, the output circuit according to the present invention reduces power consumption of the output circuit and avoids erroneous operation of the CMOS circuit.

Abstract: A rate of change comparator uses an RC charging circuit and a separate RC discharging circuit to follow a transducer output. The resistor component of each RC circuit is shunted by a diode, each biased in a different orientation so that the charging circuit charges quickly through its diode but discharges slowly through its resistor and the discharging circuit discharges quickly through its diode and slowly through its resistor. The difference in output between the charging and discharging circuits is detected with a comparator, biased off by a threshold bias voltage developed from one of the circuits. The comparator is unaffected by slow changes in transducer signals due to drift, ambient condition and similar changes because the differential voltage between the circuits is minimized for transducer signal changes below the level set by a threshold bias level.