Abstract: A process for manufacturing isolated semi conductor components in a semi conductor wafer of the type used in bipolar technology. In this process, polycrystalline silicon is deposited in a recess in a silicon substrate whose walls are insulated by a silicon nitride layer except for an opening formed in this nitride layer at the bottom of said recess. Then, the polycrystalline silicon is re-epitaxied so as to become monocrystalline silicon by thermal heating from the "nucleus" formed by the underlying silicon in said opening.

Abstract: In a method for manufacturing a semiconductor memory device, a semiconductor chip and an adhesive tape having an adhesive layer are prepared. The adhesive layer comprises a polyamic acid intermediate derived for example from a pyromellitic dianhydride and a diamine. The adhesive tape is pressed onto the semiconductor chip at a temperature of from about 250.degree. C. to about 400.degree. C. for a predetermined time period such as 2 to 5 sec.

Abstract: A method of making a silicon diaphragm pressure sensor includes forming an oxide film on one surface of a monocrystalline silicon substrate. A polycrystalline silicon layer is formed on the oxide film. The oxide film may be partly removed before the formation of the polycrystalline silicon layer. The polycrystalline silicon layer is heated and melt to recrystallize the same, thereby converting the polycrystalline silicon layer into a monocrystalline silicon layer. On the monocrystalline silicon layer may be epitaxially grown an additional monocrystalline silicon layer. By using the oxide film as an etching stopper, a predetermined portion of the substrate is etched over a range from the other surface of the substrate to the oxide film, thereby providing a diaphragm of the pressure sensor.

Abstract: A semiconductor laser having mirror faces serving as resonators, in which the active laser region (2) includes end zones adjoining the mirror faces which have implanted ions, preferably protons, with associated crystal damage. The end zones have a length which is at least equal to the diffusion length of the recombining charge carriers in the end zones. As a result of the high recombination rate in the end zones substantially no non-radiating recombination occurs at the mirror faces so that mirror erosion is avoided.The invention relates to a method in which the end zones are formed by an ion bombardment on the upper surface of the semiconductor wafer with a number of lasers, which wafer at the area of the mirror (cleavage) faces to be formed is provided with grooves which do not extend up to the active layer, in which grooves the end zones are provided via an ion bombardment through the active layer.

Abstract: A method of manufacturing a semiconductor device comprises a step of preparing a semiconductor substrate (12) having a surface layer of silicon, a step of forming a conductive thin film (14) of a silicide composed of a metal having a high melting point and silicon on the semiconductor substrate (12), a step of forming an oxidation-resistant mask (18) on a first portion (14a) of the conductive thin film (14) and a step of converting a second, exposed, portion (19) of the conductive thin film (14) into an insulating film (19a) of a composite oxide composed of silicon oxide and an oxide of the subject metal by oxidizing the exposed portion (19) while maintaining the first portion (14a) of the conductive thin film (14) covered by the mask (18).

Abstract: The surface of a substrate which includes a plurality of photovoltaic junctions spaced along it is prepared as follows: a first anodic oxide layer is formed to cover the whole surface of the substrate and ensures perfect control of the photovoltaic junctions, a second layer is deposited of metal which is impervious to the radiation to be detected, then through photolithography, only the zones of the second layer that it is desired to render impervious to the radiation to be detected are maintained and the remainder removed; and finally, a layer of dielectric material is deposited to cover the whole surface.

Abstract: A method for manufacturing a plastic IC package with a light receiving window, for a semiconductor IC device, which includes the steps of preparing a lead frame supporting member provided, in a central portion of a main surface thereof, with a groove for receiving a liquid molding resin therein, disposing an IC lead frame on the lead frame supporting member within a mold, and molding a plastic package so as to enclose the IC lead frame and the lead frame supporting member therein and to form an opening in the plastic package at a portion corresponding to the IC chip mounting area of the IC lead frame. An IC chip is then mounted on the IC chip mounted area and interconnected by wires with the leads of the IC lead frame. Then a light transmitting window plate is adhesively fixed over the opening in the molded plastic package.

Abstract: An imaging array of the charge transfer type having improved sensitivity is disclosed. The array includes a plurality of substantially parallel charge transfer channels with channel stops therebetween which extend a distance into a semiconductor body. At least some of the channel stops have blooming drains therein for the removal of excess photogenerated charge. The improvement comprises potential barrier means which constrain electrical charge generated by absorption of light in the body to flow into the channels while preventing the loss of such charge by direct flow to the blooming drains. Potential barrier means include buried barrier regions extending a further distance into the body from those channel stops having blooming drain regions therein.The invention also includes an improved method of forming this array wherein the improvement comprises forming buried barrier regions containing a greater concentration of conductivity modifiers than the channel stops after the blooming drains are formed.

Abstract: Integrated circuits wherein the width of contacts is narrowed by a sidewall oxide, so that the metal layer can be patterned to minimum geometry everywhere, and does not have to be widened where it runs over a contact.

Abstract: A method of manufacturing a MOS device wherein a semiconductor substrate is selectively etched to form a groove in a field region and an element formation region surrounded by the groove such that an angle .theta. is formed between a wall of the groove and a first imaginary extension of a top surface of the element formation region, the angle .theta. satisfying the relation, 70.degree..ltoreq..theta..ltoreq.90.degree.. Then, a field insulating film is deposited in the groove, and a MOS transistor is formed in the element formation region. The element formation region has source, drain and channel regions of a field effect transistor therein and a gate electrode formed on a gate insulating film on the channel region. The gate electrode extends onto the surface portion of the field insulating film.

Abstract: A fuse programmable ROM includes a wafer for a CMOS-type structure having an emitter, which emitter is overlain by a fuse pad of an undoped polysilicon and a conductive layer. There is a layer of barrier oxide disposed on the conductive top layer of the fuse pad and a sidewall oxide surrounding the periphery of the fuse pad both of which are overlain by the metallic electrical connection.The process of producing the fuse programmable ROM includes wide utilization of standard CMOS fabrication techniques with which are included the steps of depositing fuse material of undoped polysilicon, forming the fuse material into a fuse pad, and then making an electrical connection with the fuse pad.

Abstract: This invention relates to a process of manufacturing an integrated structure in which optical signals can be processed in an electrooptic material such as lithium tantalate and electrical signals can be processed in a semiconductor material such as silicon. Microelectronic semiconductors are fabricated in the semiconductor material and electrooptic devices are fabricated in the electrooptic material. Devices made by the process of the present invention are also disclosed.

Abstract: A multiple-zone junction termination extension region is formed adjacent a reverse-blocking junction in a semiconductor device to increase the breakdown voltage of such device. A single mask is used to form the multiple-zone JTE region, with the mask having different patterns of openings in the different zones of the mask. Adjacent openings are maintained with a center-to-center spacing of less than 25 percent of the depletion width of the reverse-blocking junction in a voltage-supporting semiconductor layer adjoining the reverse-blocking junction at the ideal breakdown voltage of the junction. As a consequence, the resulting non-uniformities in doping of the various zones of the JTE region are negligibly small. An alternative JTE region is finely-graduated in dopant level from one end of the region to the other, as opposed to having multiple zones of discrete doping levels.

Abstract: A CMOS EPROM is made wherein the typical EPROM device is an N-channel IGFET having a control gate self-aligned with an underlying floating gate. In this process the EPROM floating gate and the gates of both the P-channel and N-channel peripheral circuit transistors are formed from a first deposited polysilicon layer. The EPROM control gate is formed from a second deposited polysilicon layer. This CMOS EPROM process employs a surprisingly few photoresist steps and is compatible with a high temperature oxidation step for making a very high quality intergate polysilicon oxide in the EPROM devices.

Abstract: The gate electrode in an inverted field effect transistor (FET) is fabricated with titanium to provide an FET which is particularly suitable for use as the switching element in a matrix addressed liquid crystal display. More particularly, the resist employed in gate electrode patterning is plasma ashed in an oxygen atmosphere to toughen the titanium gate material and render it more amenable to subsequent processing steps.

Abstract: An insulated-gate semiconductor device, such as an IGFET or IGT, with improved source-to-base shorts includes, in a semiconductor wafer, a drain region, a voltage-supporting region, a base region, and a source region. Generally parallel gate fingers of refractory material are insulatingly spaced above the wafer. Elongated base portions are provided between, and preferably registered to, a respective pair of adjacent gate fingers. Elongated source portions are each situated within a respective base portion and each is preferably registered to a respective pair of adjacent gate fingers. Generally parallel shorting portions are included in the wafer and are oriented transverse to the gate fingers, whereby the shorting portions can be formed without a critical alignment step. The shorting portions adjoin the base portions and also a source electrode so as to complete source-to-base electrical shorts.

Abstract: Electrolytic capacitor cells of paste electrode type are formed integrally in a composite or laminated belt in a predetermined pattern and subsequently severed or otherwise separated therefrom to provide a plurality of individual cells or stacked cell sets of desired shape. The belt includes at least one inner sheet of ion conducting/electron insulating material, outer sheets of electron conducting material, and intermediate sheets of insulating gasket material respectively interposed between the inner sheet and respective outer sheets. Each intermediate sheet has a plurality of holes arranged in a predetermined pattern and aligned with the holes in the other intermediate sheet for accommodating respective electrodes of a like number of pairs which have opposite surfaces in operative contact with the inner and respective outer sheets.

Abstract: An integrated quantum well laser structure which has a plurality of quantum well lasers for providing a plurality of light beams each having a different wavelength for use in wavelength division multiplexing.

Abstract: A method of epitaxying layers on a semiconductor substrate through apertures in an insulating layer formed on a substrate. The layers are grown from the substrate and extend on the insulating layer by reacting dichlorosilane, hydrogen chloride and a carrier gas flow in a chamber under reduced pressure. The layers are used for semiconductors device formation.

Abstract: Disclosed is a method of stabilizing and standardizing semiconductor wafers obtained from a plurality of vendor sources for use in both unipolar and bipolar device manufacturing lines. Based on measured initial oxygen concentration, the as-received wafers are grouped into lots. Next, based on measured oxygen precipitation rate of each lot, the wafer lots are grouped into classes, regardless of their vendor origin. Typically, the grouping consists of three classes corresponding to low, intermediate and high oxgen precipitation rate.The wafers of each class are then subjected to a thermal adaptation cycle tailored to the class to generate in each wafer clusters of a concentration corresponding to a predetermined cluster concentration range and a defect-free zone corresponding to a predetermined defect-free zone range. The thermal adaptation cycle is different from class to class, but identical for wafers of a given class.