Abstract: An avalanche photodiode includes a region of second conductivity type extending a distance into a substrate and a region of first conductivity type extending a further distance into the substrate of first conductivity type with a P-N junction therebetween. The invention is a method for fabricating an avalanche photodiode having a specified breakdown voltage. The method includes the step of measuring the concentration of the first type conductivity modifiers and removing a portion of the surface of the substrate prior to forming the region of second conductivity type. This method provides control of the concentration of the first type conductivity modifiers at the P-N junction and thereby controls the breakdown voltage.

Abstract: A new technique for forming CMOS custom logic circuits is disclosed wherein standard cells (10,12,14) are used and the prior art technique of field oxide isolation (16) is replaced with transistor isolation (68-71). That is, the boundaries (18,20,22,24) between the cells are formed by transistors that are permanently "off", i.e., tied to the positive or negative voltage supply, depending on whether the transistors are p-channel or n-channel devices, respectively. Therefore, instead of having to deposit separate p+ and n+ source/drain diffusions for each cell, as in the prior art, a single p+ diffusion strip (60) and a single n+ diffusion strip (62) are utilized, where the polysilicon mask of both the logic and isolation transistors defines the cell sizes. Thus, the p+ and n+ diffusions become generic steps which do not vary from circuit to circuit, decreasing the turnaround time associated with custom logic circuit layout and design.

Abstract: A technique is disclosed for the artificial introduction of a localized subsurface strained layer within a thick polysilicon layer to minimize the large change in warpage (defined as springback) which occurs in a (100) Si substrate thinning operation during the mechanical processing of dielectrically isolated (DI) wafers. This novel technique is capable of favorably altering the state of stress and the stress profile in the multicomponent "polysilicon/SiO.sub.2 /(100) Si" DI structure so as to reduce the natural springback in warpage that occurs when the stiffening member, the (100) Si substrate, is removed. This subsurface disturbed layer is retained within the polysilicon layer during subsequent processing to maintain the favorable stress profile with a minimum of wafer warpage. In one embodiment of the present invention, the subsurface strained layer is generated by growing an interface layer (SiO.sub.2 or Si.sub.3 N.sub.

Abstract: This invention discloses a semiconductor device, and method of manufacturing such device, which provides a high degree of moistureproofing, provides a high production yield, and in which defective elements can be replaced by the use of fuses. A circuit test of the device is conducted while at least part of each of a fuse and a bonding pad is exposed through a first passivation film covering a semiconductor substrate on which circuit elements such as MISFETs and capacitors are formed, and any defective elements are replaced by the use of fuses. Contamination of and damage to the elements during the test can thus be prevented. Thereafter, a second passivation film is formed so as to cover all the essential portions of the fuses and bonding pads. The exposure of cracks in the fuses and bonding pads is thus prevented, and the invasion of moisture, etc., into the lower layers below the fuses and bonding pads is also prevented, thereby improving the moistureproofing and reliability of the device.

Abstract: A static RAM using a flip-flop circuit as a memory cell is disclosed. The gate oxide film of the MOS transistor for selecting the memory cell is thicker than the gate oxide film of the MOS transistor included in the peripheral circuit of the memory matrix.

Abstract: A method for automatically laying out a circuit starting from a logic gate diagram, especially for a CMOS technology. The logic is divided into blocks having a maximum number of serially connected transistors. Then the transistors are ordered to maximize the number of contiguously connected transistors. The ordered transistors then have their remaining connections determined according to the type of logic gate they represent.

Abstract: On the doped area of a monocrystalline silicon substrate is grown a thick oxide layer a side portion of which is subjected to etching and underetching within a predetermined area until it uncovers an edge of silicon on which is then grown thin oxide; polycrystalline silicon layers separated by an oxide layer are then deposited to produce a nonvolatile memory cell in which the floating gate consisting of one of said polycrystalline silicon layers is separated from the underlying doped area of the substrate, which constitutes the drain, by a very small thin oxide area which adjoins an extended area of thick oxide. The electrical capacitance between the floating gate and the drain is thus reduced with resulting smaller dimensions of the cell for given performance.

Abstract: The invention comprises an improved isolation slot in an integrated circuit structure which minimizes damage to the silicon substrate. The improved isolation slot is formed by etching a slot in the substrate of an integrated circuit structure; depositing a buffer layer in the slot adjacent the walls of the slot; and forming an isolation oxide layer in the slot over the buffer layer; whereby the presence of the buffer layer between the substrate and the isolation oxide minimizes damage to the substrate by the oxide. In a preferred embodiment, the buffer layer comprises polysilicon which is partially oxidized to form the isolation oxide layer. A barrier layer is formed between the slot walls and the polysilicon buffer layer to electrically insulate the polysilicon from the adjoining integrated circuit structure.

Abstract: A method of manufacturing a semiconductor device manufactures a semiconductor device provided with plural kinds of Schottky barrier diodes having different forward voltages on one substrate. The method includes (a) a step of forming at least one Schottky barrier diode of a first kind, and (b) a step of forming at least one Schottky barrier diode of a second kind. The step (a) is performed by placing a first metal layer at a first surface part of a silicon substrate, and then by silicifying the first metal layer. The step (b) is performed by plating, at a second surface part of the silicon substrate which is different from the first surface part of the silicon substrate, a second metal layer which consists of a metal different from the metal consisting of the first metal layer and then by silicifying the second metal layer.

Abstract: An improved package for a semiconductor device comprises an integrated circuit die and a mounting package having an array of parallel leads which directly connect perpendicular to the die. The process for making the package comprises forming an array of parallel, spaced apart, conductor pins; bonding the array of parallel conductor pins directly to an integrated circuit die while maintaining the die in a plane perpendicular to the parallel pins; and surrounding the die with a package material capable of protecting the die.

Abstract: The bird's heads of a local oxidation process are minimized by performing a polishing or grinding step to reduce the height of the bird's head down to a plane using the oxide inhibiting mask of the local oxidation process as a polishing stop.

Abstract: In a method for fabricating a thyristor in which n-type impurities are diffused in a p-base of a pnp wafer to form an n.sup.+ -emitter, the step of diffusing the n-type impurities for forming the n.sup.+ -emitter has the conditions which are set not to exceed the range where the amount of doped impurities is smaller than that which is electrically activated, thereby performing the gettering process by diffusing n-type impurities in two surfaces of the pnpn wafer in which the n.sup.+ -emitter having no defects is formed. Even if a thyristor obtained by the above processes has a high off-state voltage, it has a low on-state voltage, a short turn-off time and a small variation in a reverse recovery charge.

Abstract: A method of manufacturing optically sensitive semiconductor devices in which an anti-reflective coating is provided without the addition of mask or etch steps to the manufacturing process flow. A single layer of silicon nitride is patterned to provide an anti-reflective coating over the active area of the optically sensitive device and to form the dielectric of any capacitors also a part of the integrated circuit. An oxide passivation layer is used so that it may be opened over the active area without disturbing the anti-reflective coating.

Abstract: The wafer chuck disclosed herein is adapted to hold a semiconductor wafer during high energy treatment in a vacuum environment. The wafer is clamped by its rim to a circular domed plate so as to distort the wafer into close proximity with the domed face of the plate. Ports are provided in the face of the plate for introducing a mobile gas under controlled pressure to the interstitial space between the wafer and the domed face of the plate. An annular groove is provided around the periphery of the domed face and this groove is connected to a vacuum pumping means thereby to minimize leakage of the mobile gas into the vacuum environment.

Abstract: A method of manufacturing a semiconductor memory device having a trench memory capacitor. First masks are formed on an element forming region of a semiconductor substrate formed of the element forming region and an element isolation region. A film formed of a different material from that of the first masks is deposited and is etched by anisotropic dry etching to leave second masks around the first mask. The semiconductor substrate is selectively etched using the first and second masks as an etching mask so as to form a first groove in the element isolation region. An insulation film is buried in the first groove. A portion of the first mask, formed at least above memory capacitor forming regions in the element forming region, is removed by etching, thereby forming a third mask on a portion excluding the memory capacitor forming region.