Abstract: A bulk acoustic wave resonator with better performance and better manufacturability is described. The bulk acoustic wave resonator includes a composite piezoelectric film. The composite piezoelectric film includes a first sublayer of a first piezoelectric material, a second sublayer of a second piezoelectric material, and a third sublayer of a third piezoelectric material that is disposed between the first sublayer and the second sublayer. The first piezoelectric material has a first lattice constant, the second piezoelectric material has a second lattice constant, and the third piezoelectric material has a third lattice constant that is distinct from the first lattice constant and from the second lattice constant. The composite piezoelectric film may include a sequence of alternating sublayers of two or more distinct piezoelectric materials, or a sequence of composition graded layers having gradually changing composition.

Abstract: Aspects of this disclosure relate to a surface acoustic wave filter with an integrated temperature sensor. The integrated temperature sensor can be a resistive thermal device configured as a reflective grating for a surface acoustic wave resonator, for example. A radio frequency system can provide over temperature protection by reducing a power level of a radio frequency signal provided to the surface acoustic wave filter responsive to an indication of temperature provided by the integrated temperature sensor satisfying a threshold.

Abstract: A delay circuit provides a programmable delay and includes an input selector circuit to select between a loop delay output signal and an input signal. A loop delay circuit provides a loop delay to the input signal and supplies the loop delay output signal. The input signal can be recirculated through the loop delay circuit to extend the range of the delay. The input selector circuit selects the feedback signal during recirculation. A variable delay circuit provides a variable delay to the loop delay output signal after the recirculation is complete and supplies a variable delay output signal. An output selector circuit selects the output of the output selector circuit during the recirculation and selects the variable delay output signal after the recirculation is complete to thereby provide a delayed signal with the delay based on the loop delay, the number of loops of recirculation, and the variable delay.

Abstract: A non-reciprocal filter with parametric amplification to obtain non-reciprocal propagation of forward and reverse signals is disclosed. The non-reciprocal filter may include two asymmetrical transmission lines and a current source. The filter, when implemented in the acoustics domain using surface acoustic waves (SAW), may operate in a phase-coherent or a phase-incoherent degenerate mode, providing low insertion loss and high decibels of isolation.

Abstract: Aspects of this disclosure relate to a bulk acoustic wave device that includes a multi-layer raised frame structure. The multi-layer raised frame structure includes a first raised frame layer positioned between a first electrode and a second electrode of the bulk acoustic wave device. The first raised frame layer has a lower acoustic impedance than the first electrode. The first raised frame layer and the second raised frame layer overlap in an active region of the bulk acoustic wave device. Related filters, multiplexers, packaged modules, wireless communication devices, and methods are disclosed.

Abstract: The present invention includes a method of creating high Q empty substrate integrated waveguide devices and/or system with low loss, mechanically and thermally stabilized in photodefinable glass ceramic substrate. The photodefinable glass ceramic process enables high performance, high quality, and/or low-cost structures. Compact low loss RF empty substrate integrated waveguide devices are a cornerstone technological requirement for RF systems, in particular, for portable systems.

Abstract: An acoustic wave filter includes series arm resonators and parallel arm resonators each including an acoustic wave resonator including an IDT electrode including a pair of comb-shaped electrodes each including electrode fingers and a busbar electrode. An electrode finger connected to neither of the busbar electrodes of the pair of comb-shaped electrodes is a floating withdrawal electrode, and of all the electrode fingers of the pair of comb-shaped electrodes, the electrode finger that is connected to a same busbar electrode to which the electrode fingers on both sides thereof are connected is a polarity-reversing withdrawal electrode, and, of the series arm resonators, the series arm resonator having a lowest anti-resonant frequency includes an IDT electrode including the floating withdrawal electrodes, and the series arm resonator includes an IDT electrode including the polarity-reversing withdrawal electrodes.

Abstract: A semiconductor device or the like with a novel structure that can change the orientation of the display is provided. A semiconductor device or the like with a novel structure, in which a degradation in transistor characteristics can be suppressed, is provided. A semiconductor device or the like with a novel structure, in which operation speed can be increased, is provided. A semiconductor device or the like with a novel structure, in which a dielectric breakdown of a transistor can be suppressed, is provided. The semiconductor device or the like has a circuit configuration capable of switching between a first operation and a second operation by changing the potentials of wirings. By switching between these two operations, the scan direction is easily changed. The semiconductor device is configured to change the scan direction.

Abstract: A clock spread spectrum circuit, an electronic equipment, and a clock spread spectrum method are disclosed. The clock spread spectrum circuit includes a control circuit, a signal generation circuit, and a duty cycle adjustment circuit. The duty cycle adjustment circuit is configured to generate a target voltage having a duty cycle that is equal to a target duty cycle, the control circuit is configured to generate a frequency control word according to a modulation parameter, and the frequency control word changes discretely with time; and the signal generation circuit is configured to receive the target voltage and the frequency control word and generate and output a spread spectrum output signal that is spectrum-spread according to the target voltage and the frequency control word, and the spread spectrum output signal corresponds to the frequency control word and a duty cycle of the spread spectrum output signal is the target duty cycle.

Abstract: An RF filter (BPF) with an increased bandwidth is provided. The filter comprises a half-lattice topology and a phase shifter (PS) comprising inductively coupled inductance elements in a parallel branch parallel to a first segment (S1) of a signal path (SP) between a first port (P1) and a second port (P2) of the filter.

Abstract: In some aspects, the techniques described herein relate to a system on a chip (SoC) including a first clock divider configured to: receive an oscillator signal at a first frequency; produce, based on the oscillator signal: a first clock signal at the first frequency; and a second clock signal at a second frequency, the second frequency being a division of the first frequency. The first clock divider can selectively provide the first clock signal or the second clock signal as a first output clock signal based on a scaling configuration signal. The first clock divider can produce a frequency indication signal indicating, in combination with the first output clock signal, a start of a new clock period of the second clock signal. The SoC can include a second clock divider configured to provide a second clock output signal based on the first output clock signal and the frequency indication signal.

Abstract: Provided by a bandpass filter circuit and a multiplexer. The bandpass filter circuit includes at least one electromagnetic LC filter circuit and at least one acoustic wave resonance unit. The at least one acoustic wave resonance unit includes an input port, an output port, at least one circuit element and at least three resonators. The at least one electromagnetic LC filter circuit is electrically connected to the at least one acoustic wave resonance unit, and the at least three resonators include at least one first resonator and at least one second resonator. In a case where the at least one first resonator includes one first resonator, the first resonator is connected in series between the input port and the output port.

Abstract: Electro-acoustic resonator and method for manufacturing the same An electro-acoustic resonator comprises an acoustic mirror (120) disposed on a carrier substrate (110), a bottom electrode (130) and a piezoelectric layer (140). A structured silicon dioxide flap layer (150) is disposed on the piezoelectric layer (140), both layers having a common contact surface. Direct disposal of the silicon dioxide (150) on the piezoelectric layer (140) increases the quality factor of the resonator and leads to enhanced RF filter performance.

Abstract: A transmission line for transmitting radiofrequency range current between a first conductive element and a second conductive element, the transmission line comprising a signal current line and at least one return current line, the signal current line and the return current line(s) extending in parallel. Each current line comprises at least one first segment and at least one second segment. Each first segment is partially aligned with at least one adjacent second segment, aligned segments being separated by a first dielectric gap, and each aligned first segment and second segment forming a capacitive coupling across the first dielectric gap. This solution enables a transmission line which provides only small capacitive loading onto its surroundings, and which therefore can extend, e.g., through an antenna element without significantly affecting the performance of the antenna element.

Abstract: A clock spread spectrum circuit, an electronic equipment, and a clock spread spectrum method are disclosed. The clock spread spectrum circuit (10) includes a control circuit (11) and a signal generation circuit (12). The control circuit (11) is configured to generate a frequency control word according to a modulation parameter, and the frequency control word changes discretely with time; and the signal generation circuit (12) is configured to receive the frequency control word and generate and output a spread spectrum output signal that is spectrum-spread according to the frequency control word, and the spread spectrum output signal corresponds to the frequency control word.

Abstract: A multi-core system includes a multi-core processor, a function block, a clock management circuit, and a control circuit. The multi-core processor includes a plurality of processor cores configured to operate based on a plurality of core clock signals, respectively. The function block communicates with the multi-core processor based on an interface clock signal. The clock management circuit generates each of the plurality of core clock signals by selecting one of a first clock signal having a first frequency and a second clock signal having a second frequency different from the first frequency based on each of a plurality of frequency selection signals. The clock management circuit generates the interface clock signal based on the second clock signal. A control circuit may generate the plurality of frequency selection signals corresponding to the plurality of processor cores, respectively.

Abstract: The disclosure provides a delay estimation device and a delay estimation method. The delay estimation device includes a pulse generator, a digitally controlled delay line (DCDL), a time-to-digital converter (TDC), and a control circuit. The pulse generator receives a reference clock signal, outputs a first clock signal in response to a first rising edge of the reference clock signal, and outputs a second clock signal in response to a second rising edge of the reference clock signal. The DCDL receives the first clock signal from the pulse generator and converts the first clock signal into phase signals based on a combination of delay line codes. The TDC samples the phase signals to generate a timing code based on the second clock signal. The control circuit estimates a specific delay between the first clock signal and the second clock signal based on the timing code.

Abstract: An integrated circuit is provided. The integrated circuit includes: a clock source configured to: generate a clock signal of the integrated circuit; at least two functional circuits; and at least two clock generators corresponding to the functional circuits and configured to: determine initial phases of the corresponding functional circuits, and generate clock signals of the functional circuits based on the clock signal of the integrated circuit and the initial phases, so as to keep the clock signals of all the functional circuits synchronized, wherein the initial phases are determined based on transmission distances, over which the clock signal of the integrated circuit is transmitted from the clock source to the functional circuits, and loads of the functional circuits.

Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may receive an indication of one or more parameters associated with management of multiple antenna groups of the UE for use in energy harvesting. The UE may transmit or receive signaling based at least in part on the one or more parameters of the multiple antenna groups of the UE. Numerous other aspects are described.

Abstract: Input impedance networks and associated methods are disclosed. An input impedance network comprises a source-terminal-pair configured to couple to a power source, a recovered-power-terminal-pair configured to couple to a power sink, a transmission line coupled to the source-terminal-pair that comprises M sections, and N clamping circuits. Each of the N clamping circuits is configured to clamp at least one of voltage or current in one of the M sections, and a power recovery circuit is coupled to the N clamping circuits to enable recovered energy to be applied to the recovered-power-terminal-pair.