Abstract: Various embodiments provide for a continuous time linear equalizer (CTLE) that includes an active inductor, which can be included in a receiver portion of a circuit. For some embodiments, the CTLE in combination with the active inductor can implement a signal transfer function comprising at least two zeros and two poles.

Abstract: An apparatus includes a sample-and-hold (S/H) circuit. The S/H circuit includes a first switch coupled to provide an input signal to be sampled, and a second switch coupled to the first switch and to a first capacitor. The S/H circuit further includes a third switch coupled to the second switch and to a second capacitor, and a fourth switch to selectively couple to ground a node between the first and second switches.

Abstract: An integrated circuit includes: a clock domain having a clock domain input; and clock management logic coupled to the clock domain. The clock management logic includes: a PLL having a reference clock input and a PLL clock output; a divider having a divider input and a divider output, the divider input coupled to the PLL clock output; and bypass logic having a first clock input, a second clock input, a bypass control input, and a bypass logic output, the first clock input coupled to divider output, the second clock input coupled to the reference clock input, and the bypass logic output coupled to the clock domain input. The bypass logic selectively bypasses the PLL and divider responsive to a bypass control signal triggered by a reset signal. The reset signal also triggers a reset control signal delayed relative to the bypass control signal.

Abstract: Systems and methods are provided for a clock generator is configured to generate N clock signals evenly spaced by phase. A clock generator includes a poly phase filter configured to utilize a differential clock signal to generate N intermediate signals, the intermediate signals being spaced approximately 360/N degrees apart in phase. A phase error corrector is configured to receive the intermediate signals and to generate N clock output signals, where a phase error is a measure of a difference in phase between consecutive ones of the clock output signals from 360/N degrees, the phase error corrector being configured to reduce phase error among the clock output signals based on a feedback signal. A phase error detection circuit is configured to receive the clock output signals and to generate the feedback signal based on detected phase errors among the clock output signals.

Abstract: The application provides an apparatus, a system, a detector and a detection method for power supply voltage detection.

Abstract: Foreign substance detection can be performed with a simple configuration in a power transmission system. A power transmitting apparatus that wirelessly transmits power to a power receiving apparatus, the power transmitting apparatus comprises: determination means for, in a case where an initial impedance value and the detected output impedance value do not match and there is no change in the output impedance value between before and after the transmission of a predetermined detection signal, determining that a foreign substance is present within a predetermined power transmission range, and, in a case where the initial impedance value and the detected output impedance value do not match and there is a change in the output impedance value between before and after the transmission of the predetermined detection signal, determining that a power receiving apparatus is present within the predetermined power transmission range.

Abstract: The switch device includes a first circuit. The first circuit has a first end coupled between a first terminal and a second terminal, and the first circuit has the second end coupled between the first terminal and the second terminal or coupled to a third terminal. The first circuit includes a first switch and a second switch. The first switch is coupled between the first end and the second end of the first circuit and is turned on or off according to a first control signal. The second switch is connected to the first switch in parallel and is turned on or off according to a second control signal. The first switch and the second switch include transistors of the same type. In a surge protection mode, the second switch is turned on to dissipate the surge current.

Abstract: A device for detecting stray electrical currents in fluid mediums comprises at least two probes for partially disposing in a fluid medium and a control unit. The control unit comprises at least one analog-to-digital signal converter in electrical communication with at least one of the probes, at least one audio-visual alarm, and a processor operably coupled to the at least one converter and to the at least one audio-visual alarm. The processor is operable to measure an electrical potential difference between the two probes, to calculate at least one frequency-dependent characteristic associated with a plurality of said measurements, and to transmit an alert signal if the at least one frequency-dependent characteristic satisfied a threshold. Advantageously, by monitoring for the frequency, the device more consistently and more reliably detects the presence of stray alternating currents.

Abstract: A micro-energy acquisition device is provided. The radio frequency circuit generates a ground voltage according to the micro-energy voltage and output the ground voltage through the ground terminal; the first unidirectional conduction component makes the ground voltage to be unidirectionally conductive to generate the first voltage; the microprocessor generates the supply voltage according to the first voltage and is operated according to the supply voltage; the first input/output port of the microprocessor is connected with the first unidirectional conduction component; since the microprocessor and the radio frequency circuit are connected in series, an electrical energy consumption speed of the micro-energy voltage is slower, the capability of data transmission is improved and an error rate of data transmission is reduced.

Abstract: Embodiments herein describe a self-biased divider for a clock in an integrated circuit. In one embodiment, the clock includes a VCO that generates a clock signal that is output to the self-biased divider. However, because the VCO may generate an analog clocking signal (e.g., a low amplitude sine wave of unknown common mode) to reduce jitter, the amplitude can vary which means it may not sufficiently track CMOS parameters. The clocking signals generated by the self-biased divider are used as feedback signals for DC biasing (or DC leveling). In this manner, the divider is referred to a self-biased divider since signals generated by the divider are used to perform DC biasing/leveling.

Abstract: A door system comprises a door frame adapted to be mounted within an opening, a door pivotally attached to the door frame, an AC/DC converter operably associated with the door frame, a DC electric device mounted to the door, at least one sensor mounted to the door frame or the door, and a power management controller configured to receive an input from the at least one sensor and send a command to the DC electric device. The AC/DC converter is configured to be electrically connected to an AC power unit disposed outside the door system. The DC electric device is electrically connected to the AC/DC converter.

Abstract: A switch device includes a first radio-frequency (RF) terminal, a second RF terminal, a first transistor, a second transistor, and a variable resistance element. The first transistor includes a first terminal coupled to the first RF terminal, a second terminal, and a control terminal coupled to a control signal terminal providing a control signal. The second transistor includes a first terminal coupled to the second terminal of the first transistor, a second terminal coupled to the second RF terminal, and a control terminal. The variable resistance element is coupled between the second terminal of the first transistor and a bias voltage terminal. When the first transistor and the second transistor are in a transient state, the variable resistance element provides a lower resistance. When the first transistor and the second transistor are in an ON state, the variable resistance element provides a higher resistance.

Abstract: Reduction in power consumption of a semiconductor device is achieved. The semiconductor device includes: a first circuit operating at a first power supply voltage and a second circuit operating at a second power supply voltage and including a level shift unit and a switch unit, the first circuit is configured of a low-breakdown-voltage n-type transistor that is an SOTB transistor, and the switch unit is configured of an n-type transistor that is an SOTB transistor. A second power supply voltage is higher than a first power supply voltage, and an impurity concentration of a channel formation region of the n-type transistor is higher than an impurity concentration of a channel formation region of the low-breakdown-voltage n-type transistor.

Abstract: A semiconductor apparatus includes an internal dock generating circuit, a stop controlling circuit, and a data dock generating circuit. The internal clock generating circuit generates, based on a reference clock signal, a plurality of internal clock signals. The stop controlling circuit generates a stop signal and a dock level signal based on the reference clock signal and the plurality of internal clock signals. The data clock generating circuit generates a data clock signal and a complementary data clock signal based on the plurality of internal clock signals, the stop signal, and the clock level signal.

Abstract: A key reuse circuit is provided, a key component is used to generate a DC voltage and a startup-trigger-signal according to a user input, the switch circuit generates a key trigger signal according to the DC voltage, the control circuit reverses a level of an enable-regulation-signal when a time duration of the key trigger signal is longer than or equal to a preset time duration, or determines a key value of the key component when the time duration of the key trigger signal is shorter than the preset time duration, the power on/off regulation circuit generates a voltage-conversion-enable-signal according to the startup-trigger-signal and an enable-regulation-signal having a first level, the buck circuit generates a first voltage according to the power voltage and the voltage-conversion-enable-signal and stops generating the first voltage when the voltage-conversion-enable-signal is terminated, so that reuse of a general key in the key matrix is realized.

Abstract: A wearable device charging system comprising a base station and a wearable charging unit. The wearable charging unit configured to couple with, and charge, a wearable item while the wearable item is in an as-worn position. The wearable charging unit comprising a housing, a battery, and a charging system. The charging system may comprise an inductive charging system or a conductive charging system. The base station including a charging system for charging the wearable charging unit and a power input for coupling with an external power supply.

Abstract: Circuits and methods that provide wider bandwidth and smaller IM inductances for phase change material (PCM) based RF switch networks. The present invention recognizes that it is beneficial to consider the total high parasitic capacitance to ground of the various PCM switches in an RF switch network as constituting two or more separate capacitive contributions. This leads to several “split capacitance” concepts, including signal-path splitting, switch-block splitting, stacked-switch splitting, and splitting parasitic capacitances due to layout discontinuities, in which compensating impedance matching inductances are inserted between additive capacitances.

Abstract: Disclosed herein is an apparatus that includes a driver circuit including a plurality of first transistors arranged in a first direction; a control circuit including a plurality of second transistors arranged in parallel to the plurality of first transistors, each of the plurality of second transistors being coupled to control an associated one of the first transistors; and a power gating circuit arranged between the driver circuit and the control circuit, the power gating circuit being configured to supply a first power potential to each of the plurality of first transistors.

Abstract: Analog calibration (ACAL) circuits supporting iterative measurement of an input signal from a measured circuit, and related methods are disclosed. The ACAL circuit includes a voltage reference generation circuit and a comparator circuit. The voltage reference generation circuit is configured to provide an input reference voltage. The comparator circuit is configured to compare the input reference voltage to an input circuit voltage of a measured circuit and generate a digital measurement signal based on the comparison. To provide for the ACAL circuit to more precisely measure the input circuit voltage, the voltage reference generation circuit is programmable and is configured to a generate the input reference voltage based on a programmed reference voltage selection. In this manner, the ACAL circuit can be used to measure the input circuit voltage in an iterative manner based on different programmed input reference voltages for a more precise measurement of the input circuit voltage.

Abstract: A fast-switching power management circuit operable to prolong battery life is provided. The power management circuit includes a voltage circuit that can generate an output voltage for amplifying an analog signal in a number of time intervals and a pair of hybrid circuits each causing the output voltage to change in any of the time intervals. A control circuit is configured to activate any one of the hybrid circuits during a preceding one of the time intervals to cause the output voltage to change in an immediately succeeding one of the time intervals. By starting the output voltage change earlier in the preceding time interval, it is possible to complete the output voltage change within a switching window in the succeeding time interval while concurrently reducing rush current associated with the output voltage change, thus helping to prolong battery life in a device employing the power management circuit.