Patents Examined by Joseph Kudirka
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Patent number: 9529654Abstract: A recoverable and fault-tolerant CPU core and a control method thereof are provided. The recoverable and fault-tolerant CPU core includes first, second, and third arithmetic logic circuits configured to perform a calculation requested by the same instruction, a first selector configured to compare calculation values output from the first, second, and third arithmetic logic circuits by the same instruction, determine as a normal state when two or more of the calculation values are the same, and if not, determine as a fault state, and a register file configured to record the calculation value having the same value, when determining as the normal state in the first selector.Type: GrantFiled: November 19, 2014Date of Patent: December 27, 2016Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Young Su Kwon, Jin Ho Han, Kyung Jin Byun
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Patent number: 9523737Abstract: Methods and apparatus are provided for causing the incorrect operation (‘faults’) of digital devices such as embedded computer systems or integrated circuits. The apparatus uses a switching element to cause perturbations on the power supplies of the digital device. This apparatus can be connected to existing embedded systems with a minimal of modifications, and can insert a variety of faults into those embedded systems. Such faults can be used for verification of fault-tolerant systems or algorithms, including both safety-critical designs and cryptographic designs.Type: GrantFiled: January 4, 2015Date of Patent: December 20, 2016Assignee: NewAE Technology Inc.Inventor: Colin O'Flynn
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Patent number: 9525598Abstract: A network testing device is provided in order to validate network topology information and test various other attributes of a network. The network testing device may, in response to a command, obtain connection information from a network indicated in the command. The connection information may be compared to network topology information corresponding to the network. The network topology information may indicate which interfaces of a network device should be to be connected to which interfaces of other network devices. The network testing device may then return, in response to the command, a result of the comparison. Furthermore, the network testing device may return result of other network test performed by the network testing device on the network device.Type: GrantFiled: November 13, 2014Date of Patent: December 20, 2016Assignee: Amazon Technologies, Inc.Inventors: Paolo Gianrossi, Kevin Michael Dzierwinski, Cong Wu, Jacques Joshua Richard, Travis Steven Pepper
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Patent number: 9524213Abstract: A storage control apparatus starts, in a group of storage apparatuses that store constituent data that constitute redundant data in a distributed manner in units of a stripe, in regard to respective stripes of a plurality of stripes obtained from a group of target storage apparatuses excluding one of the storage apparatuses, a plurality of rebuilding processes for restoring the constituent data; decides, for each rebuilding process, a stripe for which the rebuilding process is to be performed next, according to access loads on the respective storage apparatuses of the group of target storage apparatuses; and obtains, for each rebuilding process, constituent data corresponding to the decided stripe from the group of target storage apparatuses and executing the rebuilding process, and executes the rebuilding process, to restore constituent data stored in the excluded storage apparatus from the obtained constituent data.Type: GrantFiled: March 18, 2015Date of Patent: December 20, 2016Assignee: FUJITSU LIMITEDInventors: Takeshi Watanabe, Kazuhiko Ikeuchi, Chikashi Maeda, Kazuhiro Urata, Yukari Tsuchiyama, Guangyu Zhou
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Patent number: 9519536Abstract: Systems and methods for generating a visual indicator based on receiving a report of a transaction processing error, the error comprising an informality in a software instruction code executed during a first attempt to process a transaction. The systems may be configured to determine a preconfigured time period for correcting the software instruction code causing the transaction processing error and compare it to the actual time it took to correct the software instruction code to determine whether the processing error was corrected within the preconfigured time period. The system and method may then generate and communicate a visual indicator based on determining whether the error was corrected within preconfigured time period.Type: GrantFiled: January 1, 2015Date of Patent: December 13, 2016Assignee: Bank of America CorporationInventor: Piyush Arora
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Patent number: 9519535Abstract: An approach for two stage log normalization is provided. The approach retrieves a message format and a plurality of parameters from one or more log files. The approach determines a classification for one or more first sequence files, wherein the one or more first sequence files includes the message format from the one or more log files. The approach determines a classification of error for the one or more first sequence files. The approach determines whether there is a high confidence in the classification of error for the one or more first sequence files. The approach determines whether there is an improvement in confidence in the classification of error from one or more second sequence files, wherein the one or more second sequence files includes the message format and the plurality of parameters from the one or more log files.Type: GrantFiled: July 17, 2015Date of Patent: December 13, 2016Assignee: International Business Machines CorporationInventors: Phillip A. J. Cooper, Jevon J. C. Hill, Fiona L. Lam, Kalvinder P. Singh
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Patent number: 9501360Abstract: A method begins by a dispersed storage (DS) processing sending representations of a read-rebuild inquiry request to storage units and receiving a decode threshold number of encoded data slices in response. The method continues with the DS processing module receiving a remaining number of slice status responses regarding a remaining number of encoded data slices. The method continues with the DS processing module decoding the decode threshold number of encoded data slices to reproduce a data segment and interpreting the remaining number of slice status responses to determine whether one of the remaining number of encoded data slices includes an error. When determining the error, the method continues with the DS processing module generating a rebuilt encoded data slice based on the reproduced data segment to replace the one of the remaining number of encoded data slices that includes the error.Type: GrantFiled: June 17, 2014Date of Patent: November 22, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Brennan James Trichardt, Jason K. Resch
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Patent number: 9501356Abstract: Back-up of data to flash memory. Data to back up is written into stripes, which are sets of pages across flash memory backup devices having the same block and page address. First metadata is embedded in each stripe indicating any blocks of the flash memory known to be bad. In response to encountering a new error in a block of flash memory during writing data to back up to a stripe, re-writing the stripe starting at the next available stripe excluding pages on the block of flash memory having the new error, writing subsequent stripes excluding pages on the block of flash memory having the new error, and embedding second metadata in the re-written and subsequent stripes indicating the location of the block having the new error. Responsive to finding no bad blocks indicated in the first metadata, initiating a write to two or more stripes simultaneously.Type: GrantFiled: August 15, 2014Date of Patent: November 22, 2016Assignee: International Business Machines CorporationInventors: Michael J. Palmer, Kelvin Wong
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Patent number: 9501404Abstract: In one embodiment, a method for back-up of data to flash memory is provided. Backed up data is organized into one or more stripes, wherein a stripe comprises a set of pages across all available flash memory devices which have a same block and page address. Responsive to encountering an error in a block of flash memory during back-up of a particular stripe of data, the particular stripe of data is rewritten starting at a next available page address and excluding a page of flash memory for the block having the error. Subsequent stripes of data in the block having the error are written to pages excluding the page of flash memory for the block having the error.Type: GrantFiled: July 29, 2013Date of Patent: November 22, 2016Assignee: International Business Machines CorporationInventors: Michael J. Palmer, Peter M. Smith, Kelvin Wong
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Patent number: 9489276Abstract: A method, system and computer program product are provided for implementing enhanced wear leveling in a stack of flash memory chips. A flash memory includes plurality of flash memory chips including a number N data chips and one or more spare chips. To even wear among the plurality of flash memory chips, a memory controller for the flash memory periodically transfers data from a data chip to a current spare chip, the current spare chip becomes a data chip and the selected data chip becomes the current spare chip. Over time, each chip in the stack becomes the spare chip. If a chip becomes nonfunctional, whatever chip is currently the spare chip becomes a permanent data chip and no more rotating is done.Type: GrantFiled: February 20, 2015Date of Patent: November 8, 2016Assignee: International Business Machines CorporationInventors: Gary A. Tressler, Diyanesh Babu C. Vidyapoornachary
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Patent number: 9483366Abstract: In one embodiment of the present description, a copy relationship is established between a storage location at a first site and a storage location at a second site in a data storage system, wherein a dynamically assignable bitmap preset to one of a plurality of different predetermined bit patterns is selected as a function of both the availability of the selected bitmap and the type of predetermined bit pattern identified for the selected bitmap. The selected bitmap may be assigned as an out-of-sync bitmap wherein updates to the storage location at one site, which are to be copied to the storage location at the other site, are indicated in the selected bitmap, and data writes being written to the storage location at the one site, are copied to the storage location at the other site, using the selected bitmap as an out-of-sync bitmap. Other aspects are described.Type: GrantFiled: June 22, 2015Date of Patent: November 1, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Theresa M. Brown, Nedlaya Y. Francisco, Theodore T. Harris, Jr., Suguang Li, Mark L. Lipets, Carol S. Mellgren, Raul E. Saba, Alfred E. Sanchez, Warren K. Stanley
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Patent number: 9471451Abstract: A method, system and computer program product are provided for implementing enhanced wear leveling in a stack of flash memory chips. A flash memory includes plurality of flash memory chips including a number N data chips and one or more spare chips. To even wear among the plurality of flash memory chips, a memory controller for the flash memory periodically transfers data from a data chip to a current spare chip, the current spare chip becomes a data chip and the selected data chip becomes the current spare chip. Over time, each chip in the stack becomes the spare chip. If a chip becomes nonfunctional, whatever chip is currently the spare chip becomes a permanent data chip and no more rotating is done.Type: GrantFiled: June 18, 2014Date of Patent: October 18, 2016Assignee: International Business Machines CorporationInventors: Gary A. Tressler, Diyanesh Babu C. Vidyapoornachary
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Patent number: 9459991Abstract: Embodiments of the present invention provide a method, system and computer program product for heap dump object identification in a heap dump analysis tool. In an embodiment of the invention, a method for heap dump object identification in a heap dump analysis tool can be provided. The method can include instrumenting an object with a uniquely identifiable marker, instantiating the instrumented object in a virtual machine executing in memory by a processor of a host computer and triggering a heap dump in the virtual machine. The method also can include parsing a heap dump file resulting from the triggered heap dump to locate a reference to the uniquely identifiable marker. Finally, the method can include displaying an association between the object and the heap dump file in a heap dump analysis tool executing in the memory by the processor of the host computer.Type: GrantFiled: December 31, 2009Date of Patent: October 4, 2016Assignee: International Business Machines CorporationInventors: Ramratan Vennam, Patrick W. Wolf
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Patent number: 9454439Abstract: A method and system for the backup and recovery of a converged infrastructure computer system are provided with the ability to determine if the backup meets requirements of a disaster recovery plan. The method and system provide backup and recovery of the data and applications including backup and recovery of the configuration and mapping information of the converged infrastructure computer system. The backups are periodically tested to determine if they meet predetermined metrics that are specified in the disaster recovery plan.Type: GrantFiled: September 26, 2014Date of Patent: September 27, 2016Assignee: Unitrends, Inc.Inventors: Alberto Gonzalez Martos, Vernon Keith Boland, Elizabeth Campbell
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Patent number: 9454668Abstract: When a failure of a reply in response to a packet is detected, A terminal apparatus transmits, to a stand-by information processing apparatus, multiple packets in which multiple divided command statements are attached to header areas thereof, the divided command statements being obtained by dividing into multiple statements a command statement for a switch command to switch from a currently-operated information processing apparatus to the stand-by information processing apparatus. The stand-by information processing apparatus stores each of the divided command statements that are attached to the packets that are transmitted from the terminal apparatus. The stand-by information processing apparatus performs a switch operation to switch from the currently-operated information processing apparatus to the stand-by the information processing apparatus in accordance with the switch command that is generated from the stored divided command statements.Type: GrantFiled: October 29, 2014Date of Patent: September 27, 2016Assignee: FUJITSU LIMITEDInventor: Masayoshi Utaka
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Patent number: 9448896Abstract: Torn write mitigation circuitry determines if a write operation to memory is in progress at or about a time of power loss. In response to the write operation being in progress at or about the time of the power loss, the torn write mitigation circuitry causes torn write data and metadata to be stored to a non-volatile cache. The torn write data comprise data left in a degraded or uncorrectable state as a result of the loss of power. The metadata describe the torn write data.Type: GrantFiled: August 7, 2013Date of Patent: September 20, 2016Assignee: SEAGATE TECHNOLOGY LLCInventors: Mark Allen Gaertner, Jon Trantham, Vidya Krishnamurthy, Steve Faulhaber, Yong Yang
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Patent number: 9448834Abstract: An illustrative method for validating integrity of a source server backup includes receiving, at a recovery server, data indicating a state of a data storage unit associated with a source server, creating a virtual hard drive image from the received data, and storing, in memory of the recovery server, the created virtual hard drive image. The method also includes booting a virtual machine using the stored hard drive image and mounting a second drive image to the virtual machine including tools facilitating access to an operating system running on the virtual machine by an application running on the recovery server. The tools are prevented from being installed in an operating system running on the source server.Type: GrantFiled: October 27, 2015Date of Patent: September 20, 2016Assignee: Unitrends, Inc.Inventors: Alberto Gonzalez Martos, Vernon Keith Boland
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Patent number: 9448873Abstract: A method, apparatus, and/or computer program product analyzes data processing. Dependency metadata, which is used for representing dependency on data among at least two components of an application, is acquired. Error information, which is used for describing errors that occurred while running the application, and data output, which includes data output by components used to run the application, are acquired. Based on the error information, dependency metadata and data output relevant to the error information are analyzed to provide an analysis result. The analysis result includes at least one of: a reason why an error occurs, a prompt for an error correction method, a relevant dependency metadata leading to an occurrence of an error, and relevant data output leading to an occurrence of an error.Type: GrantFiled: September 11, 2014Date of Patent: September 20, 2016Assignee: International Business Machines CorporationInventors: Gang Huang, Tan Jiang, Ling Lan, Yong Yao, Li Yi, Liang Wang, Yu Zhang
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Patent number: 9436533Abstract: Some embodiments provide a system that allows application developers to track and monitor crashes that are occurring with their applications on various mobile devices. In some embodiments, the system includes an application programing interface (API) server that receives crash reports with raw crash data from the mobile devices and facilitates in assigning each crash report to one of several different crash processing servers. The crash processing server of some embodiments receives the raw crash data and translates obscure data in the raw crash data into a human or developer readable form.Type: GrantFiled: June 3, 2014Date of Patent: September 6, 2016Assignee: APTELIGENT, INC.Inventors: Sean Hermany, Paul Lappas, Andrew Levy, Robert Kwok, Andrew Yousef, Kevin Su, Keith Dreibelbis
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Patent number: 9436552Abstract: According to an aspect, a method for triggering creation of a checkpoint in a computer system includes executing a task in a processing node of the computer system and determining whether it is time to read a monitor associated with a metric of the task. The monitor is read to determine a value of the metric based on determining that it is time to read the monitor. A threshold for triggering creation of the checkpoint is determined based on the value of the metric. Based on determining that the value of the metric has crossed the threshold, the checkpoint including state data of the task is created to enable restarting execution of the task upon a restart operation.Type: GrantFiled: June 12, 2014Date of Patent: September 6, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: Chen-Yong Cher