Patents Examined by Joseph Kudirka
  • Patent number: 9218259
    Abstract: A method for testing a serial over local area network (SOL) function of a motherboard of a computing device. The method determines that the SOL function is normal if forward data can be transmitted from the serial port of the motherboard to a network interface controller (NIC) of the motherboard through a predefined path, and backward data can be transmitted from the NIC to the serial port through a predefined reverse path. The method determines that the SOL function is abnormal if the forward data cannot be transmitted from the serial port to the NIC through the predefined path, or the backward data cannot be transmitted from the NIC to the serial port through the predefined reverse path.
    Type: Grant
    Filed: November 26, 2012
    Date of Patent: December 22, 2015
    Assignees: HONG FU JIN PRECISION INDUSTRY (ShenZhen) CO., LTD., HON HAI PRECISION INDUSTRY CO., LTD.
    Inventor: Ling Yao
  • Patent number: 9218258
    Abstract: Roughly described, an integrated circuit chip comprises a plurality of peripheral circuits, each peripheral circuit connected to a respective debug unit, the respective debug unit configured to generate debug information of that peripheral circuit; and a plurality of separate stores for receiving debug information, storing debug information, and outputting debug information; wherein in response to a single trigger signal, the debug units are configured to stream their generated debug information to the plurality of separate stores; and wherein each of the plurality of separate stores is configured to receive debug information at a higher stream rate than it outputs debug information.
    Type: Grant
    Filed: July 9, 2013
    Date of Patent: December 22, 2015
    Assignee: ULTRASOC TECHNOLOGIES LTD.
    Inventor: Andrew Brian Thomas Hopkins
  • Patent number: 9218253
    Abstract: Example embodiments relate to embedded restoration memory. In one example implementation according to aspects of the present disclosure, a computing device may include a processor for executing instructions, a memory for storing instructions, a storage device having a user operating system, and a restoration memory embedded in the computing device and having a restoration module and a restoration image. The restoration operating system may exist independently of the user operating system and may be inaccessible to the user operating system. Additionally, the restoration module may cause the computing device to install the restoration image from the restoration memory onto the storage device upon the occurrence of a trigger event.
    Type: Grant
    Filed: May 30, 2013
    Date of Patent: December 22, 2015
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Anthony M. DiMarzio, Jr.
  • Patent number: 9218254
    Abstract: Systems, methods, and media for recovering an application from a fault or an attack are disclosed herein. In some embodiments, a method is provided for enabling a software application to recover from a fault condition. The method includes specifying constrained data items and assigning a set of repair procedures to the constrained data items. The method further includes detecting a fault condition on the constrained data items during execution of the software application, which triggers at least one repair procedure. The triggered repair procedures are executed and the execution of the software application is restored. In some embodiments, the restoring comprises providing memory rollback to a point of execution of the software application before the fault condition was detected.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: December 22, 2015
    Assignee: The Trustees of Columbia University in the City of New York
    Inventors: Michael E. Locasto, Angelos D. Keromytis, Angelos Stavrou, Gabriela F. Ciocarlie
  • Patent number: 9208013
    Abstract: Approaches for problem determination and resolution process cross communication are provided. Embodiments provide cross communication of a problem determination and resolution among similar data center devices. Specifically, symptoms of an error condition encountered for one data center device are captured by a first enterprise group, along with an associated resolution solution, and made available to an another enterprise group managing a commonly configured data center device, which may be faced with a similar error condition. The error signature and resolution steps captured by the first enterprise group are subsequently made available within and across multiple management domains operating within a common model (e.g., a publication-subscription system). Within this model, both the originator of the error determination and resolution (i.e., publisher), and one or more commonly configured data center devices susceptible to the same error condition (i.e.
    Type: Grant
    Filed: January 22, 2013
    Date of Patent: December 8, 2015
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Tamer E. Abuelsaad, Gregory J. Boss, Clifford A. Pickover, Randy A. Rendahl
  • Patent number: 9208010
    Abstract: For failure interval determination, a determination module determines a failure interval for transactions in a transaction queue based on a number of processed transactions. A transaction timeout module fails a first transaction in response to the first transaction not processing within the failure interval.
    Type: Grant
    Filed: July 1, 2013
    Date of Patent: December 8, 2015
    Assignee: International Business Machines Corporation
    Inventors: Vanessa R Earle, Gerard N Kimbuende, John M. Tarby
  • Patent number: 9201747
    Abstract: A real time database system configured to store database content with a plurality of data sets, the database content being partitioned in different partitions. The system comprises a plurality of master databases, each master database containing a partition of the database content, each partition being provided on a different physical storage unit and at least one replica database, each replica database containing subpartitions of the partitions stored in master databases. The system further comprises at least one distributor configured to route a request for a data set to the master database, where the data set to which the request refers to, is provided, and divide each partition into several subpartitions. Additionally, the system comprises at least one replicator, configured to generate a replica of each subpartition, and configured to store each replica on a replica database.
    Type: Grant
    Filed: November 26, 2010
    Date of Patent: December 1, 2015
    Assignee: TELEFONAKTIEBOLAGET L M ERICSSON (PUBL)
    Inventors: Jose Maria Chercoles Sanchez, Roman Ferrando Llopis
  • Patent number: 9201744
    Abstract: Disclosed here is a fault tolerant architecture suitable for use with any distributed computing system. A fault tolerant architecture may include any suitable number of supervisors, dependency managers, node managers, and other modules distributed across any suitable number of nodes. In one or more embodiments, supervisors may monitor the system using any suitable number of heartbeats from any suitable number of node managers and other modules. In one or more embodiments, supervisors may automatically recover failed modules in a distributed system by moving the modules and their dependencies to other nodes in the system. In one or more embodiments, supervisors may request a configuration package from one or more dependency managers installing one or more modules on a node. In one or more embodiments, one or more modules may have any suitable number of redundant copies in the system, where redundant copies of modules in the system may be stored in separate nodes.
    Type: Grant
    Filed: December 2, 2014
    Date of Patent: December 1, 2015
    Assignee: QBASE, LLC
    Inventors: Scott Lightner, Franz Weckesser
  • Patent number: 9195558
    Abstract: A method for comparing systems includes running, simultaneously, a first system and a second system, wherein the first system and the second system process events, collecting first data from the first system based on the processing of the events, collecting second data from the second system based on the processing of the events, wherein the second system includes at least one feature different than the first system, and performing a sequential probability ratio test based on the first data and the second data.
    Type: Grant
    Filed: May 25, 2013
    Date of Patent: November 24, 2015
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, TECHNION RESEARCH AND DEVELOPMENT FOUNDATION LIMITED
    Inventors: Robyn L. Focazio, Yefim H. Michlin, Larisa Shwartz, Maheswaran Surendra
  • Patent number: 9189355
    Abstract: A method for processing a service request, including receiving, from a client application, the service request which includes a header which includes transmission metadata and a client trace ID. An internal trace ID is appended to the service request and a request trace log including the client trace ID, the internal trace ID, and a time stamp corresponding to receiving the service request is generated. The method further includes selecting a cloud server including functionality to process the service request. The cloud server determines a dedicated computing cluster of a plurality of distributed cloud computing clusters to handle the service request and sends the service request to the dedicated computing cluster. Finally, the method includes recording, in the request trace log, an interaction of the dedicated computing cluster with the service request.
    Type: Grant
    Filed: May 21, 2013
    Date of Patent: November 17, 2015
    Assignee: Intuit Inc.
    Inventor: Tapasvi Moturu
  • Patent number: 9183069
    Abstract: A mechanism for managing failure of applications in a distributed environment is disclosed. A method includes detecting failure in an application node among a plurality of application nodes when the application node does not respond to a status message. The method further includes routing, by enterprise application nexus application processing interface (EANA) module, a first lock message to the failed application node and ancestors' nodes of the failed application node when the failed application node is an aware application node.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: November 10, 2015
    Assignee: Red Hat, Inc.
    Inventors: Filip Elias, Filip Nguyen
  • Patent number: 9176822
    Abstract: A method begins by a processing module receiving a large data file for storage in a dispersed storage network (DSN) and determining initial dispersed storage error encoding parameters. The method continues with the processing module encoding, during a first time interval of receiving the large data file, first data segments of the large data file using the initial dispersed storage error encoding parameters to produce a first plurality of sets of encoded data slices. The method continues with the processing module writing the first plurality of sets of encoded data slices to the DSN and monitoring processing of the writing to produce first write processing performance information. When the first write processing performance information compares unfavorably to a desired write performance range, the method continues with the processing module adjusting, for a second time interval, the initial dispersed storage error encoding parameters to produce adjusted dispersed storage error encoding parameters.
    Type: Grant
    Filed: July 17, 2013
    Date of Patent: November 3, 2015
    Assignee: Cleversafe, Inc.
    Inventors: Yogesh Ramesh Vedpathak, Ramin Rouzbeh, Jason K. Resch
  • Patent number: 9170889
    Abstract: The invention is a method of operating a system having multiple finite state machines and a controller. Each finite state machine enters an offline state upon detection of anomalous operation. The controller detects whether all finite state machines are offline. The controller transmits an online activation event signal to each finite state machine when all are offline. Each finite state machine evaluates entering the online state if current conditions permit. Reentering the online state includes loading a predetermined set of operating parameters. The finite state machines are responsive only to a reset event and an online activation event when in the offline state.
    Type: Grant
    Filed: August 21, 2009
    Date of Patent: October 27, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Gary L. Swoboda
  • Patent number: 9164841
    Abstract: A method begins by a dispersed storage (DS) processing module identifying an encoded data slice having an error, where a storage unit of a dispersed storage network (DSN) stores the encoded data slice. The method continues with the DS processing module sending a lock command to the storage unit. The method continues with the DS processing module determining resolution for the error of the encoded data slice, where the resolution includes one or more of: rebuilding the encoded data slice, issuing a set of delete requests to storage units of the DSN regarding a set of encoded data slices, issuing a set of undo write requests to the storage units of the DSN regarding the set of encoded data slices, and issuing a set of roll-back write requests to the storage units of the DSN regarding the set of encoded data slices.
    Type: Grant
    Filed: April 19, 2013
    Date of Patent: October 20, 2015
    Assignee: Cleversafe, Inc.
    Inventor: Jason K. Resch
  • Patent number: 9164857
    Abstract: Scalable structured data store operations can include logging a number of detected corrupted records within a scalable structured data store, repairing the number of corrupted records within a number of nodes of the scalable structured data store, and predicting hardware failure based on the logged number of corrupted records.
    Type: Grant
    Filed: January 30, 2013
    Date of Patent: October 20, 2015
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Matthew P. Houseman, Jun Li, Colin Heng Fai Tsui, Alvin Cheng-Tser Chen, Ajay Dhar
  • Patent number: 9158646
    Abstract: Provided is an abnormal information output system for a computer system, wherein the computer system includes at least a plurality of hardware devices and a plurality of sensors for detecting operation statuses of each hardware device. The abnormal information output system includes at least a latch module connected to each of the sensors and the hardware devices, wherein the latch module is configured to latch operation status information of the hardware devices when abnormal operation of the computer system is detected; and a basic input-output system (BIOS) module embedded in the computer system and the BIOS module is connected to the latch module and configured to analyze the latched operation status information when the computer system returns to a normal operation so as to output corresponding abnormal information. Accordingly, the computer system is capable of recording a chip failure and information regarding reasons for system failure.
    Type: Grant
    Filed: May 31, 2013
    Date of Patent: October 13, 2015
    Assignee: Celestica Technology Consultancy (Shanghai) Co., Ltd.
    Inventor: Zhirong Huang
  • Patent number: 9146798
    Abstract: In an example embodiment, a method of performing a health check on a process integration (PI) component is provided. A PI health check scenario is loaded into the PI component, the PI health check scenario including a reference to a list of checks. The PI health check scenario is then executed using the PI component, causing one or more checks in the list of checks to be performed at a predetermined frequency. The system can then automatically determine if one or more of the one or more checks fail.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: September 29, 2015
    Assignee: SAP SE
    Inventors: Vikas Gupta, Aby Jose
  • Patent number: 9141639
    Abstract: In one embodiment of the present description, a copy relationship is established between a storage location at a first site and a storage location at a second site in a data storage system, wherein a dynamically assignable bitmap preset to one of a plurality of different predetermined bit patterns is selected as a function of both the availability of the selected bitmap and the type of predetermined bit pattern identified for the selected bitmap. The selected bitmap may be assigned as an out-of-sync bitmap wherein updates to the storage location at one site, which are to be copied to the storage location at the other site, are indicated in the selected bitmap, and data writes being written to the storage location at the one site, are copied to the storage location at the other site, using the selected bitmap as an out-of-sync bitmap. Other aspects are described.
    Type: Grant
    Filed: November 1, 2013
    Date of Patent: September 22, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Theresa M. Brown, Nedlaya Y. Francisco, Theodore T. Harris, Jr., Suguang Li, Mark L. Lipets, Carol S. Mellgren, Raul E. Saba, Alfred E. Sanchez, Warren K. Stanley
  • Patent number: 9141496
    Abstract: Methods and devices for testing a physical layer (PHY) of an asymmetrical interconnect interface using a traffic generator/analyzer (TGA) are described. At least one special PHY test sequence is transmitted to the asymmetrical interconnect interface during link start up to place the device under test in PHY testing mode in which the TGA is used to generate and analyze data. The asymmetrical interconnect interface can then receive a configuration command and configure the asymmetrical interconnect interface in response to the configuration command. The asymmetrical interconnect interface can then use the TGA to transmit test sequences to, or receive test sequences from, e.g., a tester, on at least one identified lane of the asymmetrical interconnect device, which at least one identified lane is set by the configuration command.
    Type: Grant
    Filed: October 14, 2011
    Date of Patent: September 22, 2015
    Assignee: ST-ERICSSON SA
    Inventor: Andrei Radulescu
  • Patent number: 9141493
    Abstract: Instead of disabling PCI communication between system resources in a host computing device and I/O devices when a PCI Host Bridge (PHB) is unable to function, the host computing device may include a redundant PCI communication path for maintaining communication between the system resources and the I/O devices after a first PHB experiences an unrecoverable error. In one embodiment, the redundant PCI communication path includes a second PHB that is maintained in a standby state so long as the first PHB is functioning normally. However, once the first PHB experiences an unrecoverable error, the second PHB is changed to the master state and assumes the responsibility for maintaining communication between the system resources and the I/O devices.
    Type: Grant
    Filed: July 12, 2013
    Date of Patent: September 22, 2015
    Assignee: International Business Machines Corporation
    Inventors: Jesse P. Arroyo, Srinivas Kotta, Anjam Kumar Guttahalli Krishna