Abstract: Circuits and methods for current recycling in signal buffers for switched capacitor circuits are described. A signal buffer may be coupled to an impedance element, such as a resistor, configured to provide a desired reference voltage to the switched capacitor circuit. In some embodiments, a portion of the power absorbed by the impedance element may be recycled to power one or more additional circuit. Such additional circuit(s) may include active elements. In some embodiments, the switched capacitor circuit is part of an analog-to-digital converter. In some embodiments, the additional circuit(s) are also part of the analog-to-digital converter.

Abstract: An inverted-F antenna includes a ground portion, a connecting portion, and a radiating portion, wherein the ground portion is adapted to be electrically connected to a ground line; the connecting portion is respectively connected to the ground portion and the radiating portion to respectively form two included angles therebetween; the radiating portion is separated from the ground portion by a distance due to the connecting portion; the radiating portion has a transceiving segment and a feed-in segment which are mutually connected, wherein the transceiving segment receives and transmits wireless signals in a specific frequency band, while the feed-in segment is adapted to be electrically connected to a signal line; a first notch and a second notch are formed on a side of the transceiving segment, wherein the feed-in segment extends from a portion between the first and the second notches. Whereby, the inverted-F antenna provides an omnidirectional radiation effect.

Abstract: Integrated antenna structures described herein may include planar inverted-F antennas (PIFAs) integrated with artificial magnetic conductor (AMC) metamaterials. The integrated metamaterial operatively coupled with the PIFA may function as an artificial magnetic reflector, sending all the energy radiated upwards, and thereby changing the original omnidirectional radiation pattern of the PIFA to a directional radiation pattern. The integrated antenna structures that include PIFAs and metamaterials may maintain a smaller form factor as compared to similar directional antennas, while exhibiting a suitable performance in terms of radiation efficiency, radiation pattern and impedance bandwidth.

Abstract: A two-stage successive-approximation-register (SAR) analog-to-digital converter (ADC) comprising is described. The SAR ADC includes a first stage comprising a SAR ADC; a voltage-to-time interface that translates a voltage-domain residue from the SAR ADC to a time-domain residue; and a second stage comprising a time-to-digital converter (TDC) that resolves multiple bits from the time-domain residue.

Abstract: A computer-implemented method, system, and apparatus for storing binary data is disclosed. A processor receives a digital bit stream and transforms the digital bit stream to an encoded digital bit stream. The encoded digital bit stream comprises a data message encoded by an OCTS-expanded table for storage. The processor stores the encoded digital bit stream on a digital data storage device or system.

Abstract: A system to convert between analog and digital signals, in some embodiments, comprises: a differentiator to produce a differentiated signal based on an input signal and a feedback signal; an integrator, coupled to the differentiator, to integrate the differentiated signal; a quantizer, coupled to the integrator, to quantize the integrated signal; and a low-pass feedback filter, coupled between an output of the quantizer and an input of the differentiator, to generate said feedback signal using the quantized signal, wherein the low-pass feedback filter pushes at least some noise of the quantized signal downward in the frequency spectrum.

Abstract: Concentric shapes (e.g., discs and rings), are nested and displaced from a central plate. The discs are individually positioned by means of mechanical or electro-mechanical actuators such that the over-all result approximates a spherical surface reflector antenna having an adjustable radius of curvature, with the radii of curvature being equivalent to the focal length of the antenna. Another innovation includes reducing the dimensional positioning of the various discs by a modulo of the wavelength of the operating frequency of the antenna, thus reducing the throw accommodation of the actuators to only one wavelength. Each of the discs and the central plate are designed to have substantially the same area, as a nominal configuration. The accuracy of the approximation is improved as the number of discs is increased; however, very acceptable performance is obtained with as few as ten discs when compared to a perfect spherical surface.

Abstract: A method can be used to generate a reference clock signal having a reference frequency. N clock sub-signals are generated, where N is greater than or equal to 2. The N clock sub-signals are successively mutually shifted out of phase by ?/N and each clock sub-signal has an elementary frequency that is equal to the reference frequency divided by N. The N clock sub-signals are propagated over propagation paths. The elementary frequency and a length of the longest propagation path are chosen so that each sub-signal has an acceptable degree of deformation. The duration of each sub-signal edge is longer than quarter of the period of the reference frequency. The reference clock signal is generated by EXCLUSIVE OR combining the propagated clock sub-signals at the end of their respective propagation paths.

Abstract: An embodiment includes an analog-to-digital converter device. A device may include a first track and hold amplifier configured to receive an analog input signal. The device may also include a plurality of paths coupled to an output of the first track and hold amplifier. Each path of the plurality of paths includes a second track and hold amplifier coupled to the first track and hold amplifier, and a successive approximation register analog-to-digital converter coupled to an output of the second track and hold amplifier. The successive-approximation analog-to-digital converter may include heterojunction bipolar transistors, a comparator, R-2R DAC, and a SiGe BiCMOS quasi-CML SAR register and sequencer.

Abstract: Described is an analog to digital converter (ADC) which comprises: a sigma-delta modulator to receive an analog signal, the sigma-delta modulator operable to perform chopping to cancel common-mode noise; and one or more counters coupled to the sigma-delta modulator to generate a digital code representative of the analog signal.

Abstract: An analog to digital converter (ADC) circuit includes a first stage for converting a first analog voltage signal to a first digital signal including a first portion of a digital output signal representing the first analog voltage signal, and generate a first residue voltage based on the first analog voltage signal and the first digital signal. A first amplifier control unit generates a first amplifier start signal based on a second stage ready signal indicating that a second stage is ready to process a second analog voltage signal. In response to the second stage ready signal, a first amplifier generates the second analog voltage signal based on the first residue voltage. The second stage is configured to generate the second stage ready signal, receive the second analog voltage signal, and convert the second analog voltage signal to a second digital signal including a second portion of the digital output signal.

Abstract: An error feedback system for a delta sigma modulator is disclosed. The error feedback system has an error transfer function where at least k?1 coefficients are set to zero. This allows the error feedback system to be divided into k feedback paths that are performed in parallel at a clock speed that is 1/k of the system clock of the delta sigma modulator (i.e. the rate at which the output of the delta sigma modulator changes).

Abstract: Methods, systems and devices for dynamically controlling resolution of an analog-to-digital converter (ADC). The ADC receives an analog input signal and outputs digital data. A statistical unit coupled to the ADC obtains samples of the output signal and transmits a control signal to the ADC to adjust the resolution of the ADC. The control signal is generated by the statistical unit based on a comparison of at least one performance indicator with a target performance level. The at least one performance indicator is calculated using the samples.

Abstract: A display device that may compensate for characteristic deviations among pixels and impact picture quality is provided. The display device includes a plurality of pixels, a plurality of sensing lines connected to the pixels, a sensing circuit configured to extract characteristic information of the pixels through the sensing lines. The sensing circuit includes a plurality of analog-to-digital converters (ADC) to convert the characteristic information into digital sensing data and to output the digital sensing data. A compensating circuit is configured to compare output values of the plurality of ADCs, to set a correction value, and to convert first data into second data based on the sensing data and the correction value. A data driver is configured to generate data signals corresponding to the second data and to output the data signals to the pixels.

Abstract: The following description is directed to decompression using cascaded history buffers. In one example, an apparatus can include a decompression pipeline configured to decompress compressed data comprising code words that reference a history of decompressed data generated from the compressed data. The apparatus can include a first-level history buffer configured to store a more recent history of the decompressed data received from the decompression pipeline. The apparatus can include a second-level history buffer configured to store a less recent history of the decompressed data received from the first-level history buffer.

Abstract: A processor includes a first encoder configured to encode a regular bin block including at least one regular bin, a second encoder configured to encode a bypass bin block including at least one bypass bin, and a parameter calculating module comprising parameter calculating circuitry configured to determine context information for encoding the regular bin block and to transmit the context information to the first encoder. The first encoder and the second encoder may process the regular bin block and the bypass bin block simultaneously and in parallel during at least part of a specific processing cycle.

Abstract: Methods, devices, and computer programs are provided for character conversion. An original file is compressed, for instance, by a source or target device, to obtain a compressed file. Then, characters in the compressed file are converted from a source code page to a target code page to obtain a converted compressed file. The converted, compressed file may, where applicable, be sent to a target device. Also, the target device may decompress the converted compressed file to obtain a file in the target code page.

Abstract: A high-speed successive approximation analog-to-digital converter of two bits per cycle, includes three switches, two capacitor arrays, three comparators, an encoding circuit, a first switch array corresponding to the first capacitor array, a second switch array corresponding to the second capacitor array, a shifting register and a digital correction unit. The analog-to-digital converter, featuring doubled speed, realizes a successive approximation process without any fault when a high-bit large capacitor is unsettled. Thus no redundancy bit capacitor is required to compensate for unsettled pre-stage large capacitor. By using the encoding circuit, a thermometer code is converted into a binary code effectively, and inherent errors of comparators are reduced by the randomization of three comparators.

Abstract: This disclosure relates to compressing and/or decompressing a group of similar data units, such as a table or queue of data units processed by a networking device or other computing apparatus. Each data unit in the group may only have values for fields in a master set. The described systems are particularly suited for hardware-level processing of groups of sparsely-populated data units, in which a large number of the data units have values for only a small number of the fields. In an embodiment, non-value carrying fields in a data unit are compressed based on a compression profile selected for the data unit. The compression profile indicates, for each master field, whether the compressed data unit includes a value for that field. Non-value carrying fields are omitted from the compressed data unit. The compression profile also permits compression of value-carrying fields using variable-width field lengths specified in the profile.

Abstract: A successive-approximation register (SAR) analog-to-digital converter (ADC) includes a SAR circuit configured to generate a digital code based on an analog input signal. A digital-to-analog converter (DAC) is configured to convert the digital code to an analog voltage. The SAR circuit is further configured to generate a digital output signal based on a comparison between the analog input signal and the analog voltage. A first capacitor is configured to provide a reference voltage to the DAC. An adaptive charging module is configured to stabilize the reference voltage provided to the DAC by selectively connecting to a supply voltage during a first operating phase of the ADC to store a charge in the adaptive charging module and selectively connecting to the first capacitor during a second operating phase of the ADC to combine the charge stored in the adaptive charging module with a charge of the first capacitor.