Abstract: The invention relates to an encoder and a decoder and methods therein for supporting split gain shape vector encoding and decoding. The method performed by an encoder, where the encoding of each vector segment is subjected to a constraint related to a maximum number of bits, BMAX, allowed for encoding a vector segment. The method comprises, determining an initial number, Np_init, of segments for a target vector x; and further determining an average number of bits per segment, BAVG, based on a vector bit budget and Np_init. The method further comprises determining a final number of segments to be used, for the vector x, in the gain shape vector encoding, based on energies of the Np_init segments and a difference between BMAX and BAVG. The performing of the method enables an efficient allocation of the bits of the bit budget over the target vector.

Abstract: A sampled analog circuit is divided into at least two segments, each segment receiving sampled analog data and a respective subset of bits of a filter coefficient. The at least two segments can have digital-to-capacitance circuits with substantially identical ranges of capacitance values. One or more outputs from the segments can be scaled to reflect a position of the subset of bits in the bits of the filter coefficient, and thereafter added in the analog domain to produce a filtered output signal that may then be digitized. Alternatively, the outputs from the segments may be digitized before being scaled and/or added in the digital domain.

Abstract: A method of video coding using block partitioning process including a binary tree partitioning process is disclosed. The block partitioning process is applied to a block of video data to partition the block into final sub-blocks. Coding process comprising prediction process, transform process or both for the block will be applied at the final sub-blocks level. The binary tree partitioning process can be applied to a given block recursively to generate binary tree leaf nodes until a termination condition is met. In another embodiment, the quadtree partitioning process is applied to a block first. The quadtree leaf nodes are further partitioned using the binary tree partitioning process. The quadtree partitioning process can be applied to a given block recursively to generate quadtree leaf nodes until a termination condition is met.

Abstract: A clock generation circuit coupled to an integrator circuit uses a variable resistance that is adjusted in a transconductance bias feedback circuit. This resistance is calibrated to the reciprocal of the transconductance of the input amplifier. The product of the adjusted resistance and a capacitance in the clock generation circuit provides a time constant for the settling time of the integrator and controls a pulse width of an adaptively controlled duty cycle output clock.

Abstract: A compression engine and method for optimizing the high compression of a content addressable memory (CAM) and the efficiency of a static random access memory (SRAM) by synchronizing a CAM with a relatively small near history buffer and an SRAM with a larger far history buffer. An input stream is processed in parallel through the near history and far history components and an encoder selects for the compressed output the longest matching strings from matching strings provided by each of the near history and far history components.

Abstract: An A/D conversion circuit includes a reference voltage source to generate a calibration voltage, a multiplexer to receive an analog signal and the calibration voltage, and output the analog signal selected in a normal mode and the calibration voltage selected in a calibration mode or a self-diagnosis mode, an A/D converter to convert an output signal from the multiplexer into a digital signal, a non-volatile memory to hold the digital signal and calibration data, a digital calibration part to calibrate the digital signal in case of inputting the analog signal to the A/D converter in the normal mode based on the calibration data, and a self-diagnosis circuit to diagnose the A/D converter based on the digital signal in case of inputting the calibration voltage to the A/D converter in the self-diagnosis mode, and the digital signal stored in the non-volatile memory.

Abstract: A method of decoding a dynamic Huffman encoded data stream comprising receiving, by a processor, one or more input bits of encoded data from among an encoded data stream, searching, by the processor, a ternary content addressable memory (TCAM) for one or more codewords, accessing, by the processor, a plurality of random access memories (RAMs) that comprise the TCAM and have a maximum number of entries that is less than or equal to one half of two to a power of a maximum number of bits to be searched, reading a value from a first level RAM and using the value to index to a second level RAM, and outputting, by the processor, a codeword length and a decoded codeword value from either the first or second level RAM.

Abstract: In one aspect a system is provided. The system a plurality of flash compare modules to output a set of unordered output signals based on an analog input signal; a plurality of device selection modules that receive the unordered output signals and generate ordered signals representing the analog input; and a temperature and voltage compensation module for receiving one or more of temperature and voltage signals from at least a temperature and voltage sensor module that senses one or more of temperature and voltage values that are used to compensate for changes in output signals caused by changes in one or more of die temperature and core voltage.

Abstract: A circuit includes a transistor, a signal generating circuit and a noise sensing circuit. The signal generating circuit is arranged to provide an input signal. The noise sensing circuit is coupled to the transistor and the signal generating circuit, and the noise sensing circuit is arranged for receiving the input signal provided by the signal generating circuit to generate an output signal to the transistor, wherein a signal component of the output signal generated by the noise sensing circuit cancels out a signal component of the input signal provided by the signal generating circuit, and the output signal and the input signal have opposite polarities.

Abstract: The disclosure is directed to low-power high-resolution analog-to-digital converter (ADCs) circuits implemented with a delta-sigma modulators (DSMs). The DSM includes a single-bit, self-oscillating digital to analog converter (SB-DAC) and a dual-slope integrating quantizer that may replace an N-bit quantizer found in a conventional DSM. The integrating quantizer of this disclosure oscillates after quantization because the SB-DAC in the feedback path directly closes the DSM loop. The integrating quantizer circuit includes a switch at the input and two phases per sample cycle. During the first phase the switch sends an input analog signal to an integrator. During the second phase, the switch sends the feedback signal from the output of the self-oscillating SB-DAC to the integrator. The input to the SB-DAC may be output from a clocked comparator.

Abstract: A digital-to-analog converter including a resistor string configured to provide a plurality of gradation voltages formed by receiving a top voltage at one end thereof and a bottom voltage at the other end; a plurality of pass transistors including a pass transistor having one end which is electrically connected to the resistor string and outputting any one among the plurality of gradation voltages; and a decoder configured to control the plurality of pass transistors. The plurality of the pass transistors are included in any one among a plurality of groups according to values of the gradation voltages, and the pass transistors included in the any one group are divided into a first group and a second group according to output gradation voltages, and pass transistors included in the first group and pass transistors included in the second group are different types of pass transistors.

Abstract: In some data compression algorithms and/or standards, the compressed data comprises variable length symbols. A set of parallel decoders speculatively decode/decompress a window (i.e., sub-block) of data. Each of the decoders attempts to decode/decompress a symbol that starts at a different location in the compressed data block. Once the decoders have finished decoding a symbol (or determined that a valid symbol does not begin at the beginning of the window assigned to that decoder), a symbol strider selects the decoder outputs corresponding to valid symbols. The symbol strider successively selects decoder outputs based on the size of the previous symbols that were found to be valid. When the next valid symbol begins outside the current window, its location is stored to indicate the location of the next valid symbol in a subsequent window.

Abstract: The present disclosure describes aspects of current removal for digital-to-analog converters (DACs). In some aspects, a circuit for converting a digital input to an analog output includes a first resistor ladder having first resistors connectable to respective current sources and connected to a first output of the circuit. The circuit also includes second resistor ladder having second resistors connectable to the respective current sources and connected to a second output of the circuit. A common node is formed between common resistor terminals of the first resistor ladder and the second resistor ladder. Current removal circuitry is connected to the common node and referenced to an amount of current provided by the respective current sources. By removing current from the common node of the resistor ladders, common-mode current at outputs of the circuit can be reduced with minimal degradation of differential performance of the circuit.

Abstract: The present disclosure relates generally to automating the task of assignment of labels to identify electrical elements (e.g., electrode contacts, electrodes including a plurality of electrode contacts, and/or non-addressable electrical elements, like wires). A system that can automate the task of assignment of labels can include an electrical element, a microelectronic circuit associated with the electrical element, and an acquisition system. The microelectronic circuit can transmit a sequence comprising a label corresponding to the electrical element. The acquisition system can assign the label corresponding to the electrical element to a recording channel after decoding the sequence.

Abstract: Methods, apparatus and articles of manufacture (e.g., physical storage media) to calibrate interpolating string digital-to-analog converters are disclosed. Example methods disclosed herein to calibrate a digital-to-analog converter (DAC) include determining a first calibration codeword based on a first nonlinearity error value measured at an output of the DAC when a most-significant-bit (MSB) portion of an input codeword is applied to an input of the DAC. Such disclosed example methods also include determining a second calibration codeword based on a second measured nonlinearity error value measured at the output of the DAC when a least-significant-bit (LSB) portion of the input codeword is applied to the input of the DAC. Such disclosed example methods further include combining the first calibration codeword and the second calibration codeword to determine a third calibration codeword to be accessed by the DAC to calibrate the output of the DAC when the input codeword is applied to the DAC.

Abstract: A sub-ranging SAR ADC has a coarse flash ADC that generates bit values corresponding to MSBs of the digital output value, and a fine SAR ADC that generates bit values corresponding to LSBs of the digital output value. The fine ADC generates successive analog approximation signals for the analog input signal. Meta-stability (MTS) detection circuitry detects a coarse-ADC MTS condition in the coarse ADC if a magnitude of a difference between a current approximation signal and a previous approximation signal is greater than a specified threshold level. A controller controls operations of the sub-ranging ADC to correct for a detected coarse-ADC MTS condition. The MTS detection circuitry includes a positive MTS detector that detects a positive coarse-ADC MTS condition in the coarse ADC and a negative MTS detector that detects a negative coarse-ADC MTS condition in the coarse ADC.

Abstract: Methods, devices, and computer programs are provided for character conversion. An original file is compressed, for instance, by a source or target device, to obtain a compressed file. Then, characters in the compressed file are converted from a source code page to a target code page to obtain a converted compressed file. The converted, compressed file may, where applicable, be sent to a target device. Also, the target device may decompress the converted compressed file to obtain a file in the target code page.

Abstract: A circuit and a method for converting an analog signal to a digital value representation is disclosed. In one aspect, the circuit includes an incremental sigma-delta analog-to-digital converter (ADC). The circuit further includes a first input line for providing a primary analog signal representing a sensor measurement to the incremental sigma-delta ADC. The circuit further includes a second input line for providing a secondary analog signal to the incremental sigma-delta ADC. The incremental sigma-delta ADC receives the primary and secondary analog signals during a first period (TADC1) and a second period (TADC2), respectively. The circuit further includes a filter configured to weight the digital values in a sequence of digital values output by the incremental sigma-delta ADC, and to output a single digital value representing the sensor measurement.

Abstract: A device for conversion of an analog signal into a digital signal includes a clock signal generator and a ramp generator configured for delivering a rising voltage ramp. A comparator is configured for comparing the value of the analog signal and the value of the voltage ramp and for generating a comparison signal taking a first logical value when the two values are equal. A signal generator is configured for generating a counter signal equal to the inverse of the clock signal if the comparison signal takes its first value while the clock signal is in the high state, or a counter signal equal to the clock signal if the clock signal is in the low state. A counter is configured for counting the number of edges of the counter signal.

Abstract: Systems, apparatuses, and methods for compression of frequent data values across narrow links are disclosed. In one embodiment, a system includes a processor, a link interface unit, and a communication link. The link interface unit is configured to receive a data stream for transmission over the communication link, wherein the data stream is generated by the processor. The link interface unit determines if blocks of data of a first size from the data stream match one or more first data patterns and the link interface unit determines if blocks of data of a second size from the data stream match one or more second data patterns. The link interface unit sends, over the communication link, only blocks of data which do not match the first or second data patterns.