Abstract: A method of a bulk tri-gate transistor having stained enhanced mobility and its method of fabrication. The present invention is a nonplanar transistor having a strained enhanced mobility and its method of fabrication. The transistor has a semiconductor body formed on a semiconductor substrate wherein the semiconductor body has a top surface on laterally opposite sidewalls. A semiconductor capping layer is formed on the top surface and on the sidewalls of the semiconductor body. A gate dielectric layer is formed on the semiconductor capping layer on the top surface of a semiconductor body and is formed on the capping layer on the sidewalls of the semiconductor body. A gate electrode having a pair of laterally opposite sidewalls is formed on and around the gate dielectric layer. A pair of source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.

Abstract: A mounting substrate for a semiconductor light emitting device includes a thermally conductive mounting block. The mounting block has, in a first face thereof, a cavity that is configured to mount a semiconductor light emitting device therein and to reflect light that is emitted by the semiconductor light emitting device that is mounted therein away from the cavity. A conductive lead inserted into the mounting block extends into the cavity. The conductive lead is electrically isolated from the mounting block and has an exposed contact portion in the cavity. The conductive lead may be a plurality of conductive leads each having an exposed contact portion at different locations in the cavity. Related packaging methods also may be provided.

Abstract: After an amorphous semiconductor thin film is crystallized by utilizing a catalyst element, the catalyst element is removed by performing a heat treatment in an atmosphere containing a halogen element. A resulting crystalline semiconductor thin film exhibits {110} orientation. Since individual crystal grains have approximately equal orientation, the crystalline semiconductor thin film has substantially no grain boundaries and has such crystallinity as to be considered a single crystal or considered so substantially.

Abstract: A semiconductor component and a method for its production in semiconductor chip size, can have a semiconductor chip, which has external contacts of the semiconductor component that are arranged in the manner of a flip-chip on its active upper side. The semiconductor chip can be encapsulated by a plastic compound at least on its rear side and its side edges. The outer contacts, which can be arranged on external contact connecting areas, can project from the active upper side.

Abstract: An LED lamp has a package and a plurality of light emitting elements that are electrically connected to a plurality of electrode plates provided in the package and that are sealed with transparent material. A red light emitting element of the plurality of light emitting elements is wire bonded along the longitudinal direction of the package, a green light emitting element and a blue light emitting element are flip-chip bonded with its electrode faced down, and the electrodes are extended to a surface opposite to the light emission surface of the LED lamp while being embedded in the package.

Abstract: A metal oxide varistor comprising one or more zinc oxide layers is formed integral to a ceramic substrate to provide ESD protection of a semiconductor device mounted to the substrate. The portion of the ceramic substrate not forming the varistor may be aluminum oxide, aluminum nitride, silicon carbide, or boron nitride. The varistor portion may form any part of the ceramic substrate, including all of the ceramic substrate.

Abstract: The invention relates to a polymer optoelectronic device comprising at least a transparent conductive oxide layer, an active polymer layer, a back electrode layer and a substrate layer, wherein the transparent conductive oxide (TCO) layer has a controlled surface structure which is characterized by having an X-value in the range of from 10 nm to 500 nm, and a Y-value in the range of from 15 nm to 1000 nm, wherein the ratio between the X-value and the Y-value (X/Y) is at most 1, whereby the X-value is defined as the average value of the height of the peaks on the surface, the Y-value is defined as the average peak to peak distance on the surface, and both the X and Y values are measured by means of SEM (Scanning Electron Microscopy) or Atomic Force Microscopy (AFM).

Abstract: A semiconductor device is provided comprising a first potential well located within a pn junction and a second potential well not located within a pn junction. The potential wells may be quantum wells. The semiconductor device is typically an LED, and may be a white or near-white light LED. The semiconductor device may additionally comprise a third potential well not located within a pn junction. The semiconductor device may additionally comprise absorbing layers surrounding or closely or immediately adjacent to the second or third quantum wells. In addition, graphic display devices and illumination devices comprising the semiconductor device according to the present invention are provided.

Abstract: The object is to provide a lightened semiconductor device and a manufacturing method thereof by pasting a layer to be peeled to various base materials. In the present invention, a layer to be peeled is formed on a substrate, then a seal substrate provided with an etching stopper film is pasted with a binding material on the layer to be peeled, followed by removing only the seal substrate by etching or polishing. The remaining etching stopper film is functioned as a blocking film. In addition, a magnet sheet may be pasted as a pasting member.

Abstract: A semiconductor device includes a substrate having a first area and a second area adjacent to the first area, a first silicon layer provided on the substrate in the first area, a relaxed layer which is provided on the substrate in the second area and which has a lattice constant greater than a lattice constant of the first silicon layer, and a strained-Si layer which is provided on the relaxed layer and which has a lattice constant substantially equivalent to the lattice constant of the relaxed layer.

Abstract: The invention provides light emitting diode illumination source having excellent properties as an illumination source such as a flat spectral distribution in the wavelength region from green to red and a sufficient emission intensity in the red region, comprising a light emitting diode having multiple peaks with a half-value width of 20 nm or more within a range from 480 to 700 nm in a spectral distribution, wherein the minimum of the intensities of the valleys between the peaks in the wavelength range from 480 to 700 nm is 65% or more of the maximum peak intensity in the same range, and an illuminator and a backlight for a liquid crystal display using the illumination source.

Abstract: A light emitting device comprises an anode electrode layer disposed in a first direction, a cathode electrode layer disposed in a second direction different from the first direction, an emitting area with a pixel forming on an area crossed by the anode electrode layer and the cathode electrode layer and a sub-electrode layer disposed outside of the emitting area and electrically connected with at least two the anode electrode layers.

Abstract: The stack package may have a structure in which unit packages may be inserted into slots of a receiving substrate. The unit package may have a plurality of connecting pads. The receiving substrate may have substrate pads, which may be electrically connected to the connecting pads of the unit packages inserted in the slots by mechanical contact. The slots may be provided at regular vertical intervals so that the unit packages may be stacked in the vertical direction. A semiconductor module may include stack packages installed on at least one surface of a module substrate.

Abstract: A method of fabricating a semiconductor package, and a semiconductor package formed thereby, are disclosed. The semiconductor package may include one or more semiconductor die having die attach pads along a single side. The leadframe may include a plurality of elongated electrical leads, extending from a first side of the leadframe, beneath the die, and terminating at a second side of the leadframe adjacent to the bond pads along the single edge of the die. The leadframe may further include a dielectric spacer layer on the elongated leads. Spacing the semiconductor die from the elongated leads using the spacer layer reduces the parasitic capacitance and/or inductance of the semiconductor package formed thereby.

Abstract: An Assisted Charge (AC) Memory cell comprises a transistor that includes, for example, a p-type substrate with an n+ source region and an n+ drain region implanted on the p-type substrate. A gate electrode can be formed over the substrate and portions of the source and drain regions. The gate electrode can comprise a trapping structure. The trapping structure can be treated as electrically split into two sides. One side can be referred to as the “AC-side” and can be fixed at a high voltage by trapping electrons within the structure. The electrons are referred to as assisted charges. The other side of can be used to store data and is referred to as the “data-side.” The abrupt electric field between AC-side and the data-side can enhance programming efficiency. The memory cell can comprise a dual gate structure, such that the cell is a 2-bit cell.

Abstract: An (Al, Ga, In)N and ZnO direct wafer bonded light emitting diode (LED), wherein light passes through electrically conductive ZnO. Flat and clean surfaces are prepared for both the (Al, Ga, In)N and ZnO wafers. A wafer bonding process is then performed between the (Al, Ga, In)N and ZnO wafers, wherein the (Al, Ga, In)N and ZnO wafers are joined together and then wafer bonded in a nitrogen ambient under uniaxial pressure at a set temperature for a set duration. After the wafer bonding process, ZnO is shaped for increasing light extraction from inside of LED.

Abstract: A semiconductor light emitting device and a method of manufacturing the semiconductor light emitting device are provided. The semiconductor light emitting device includes a substrate, at least two light emitting cells located on the substrate and formed by stacking semiconductor material layers, a reflection layer and a transparent insulating layer sequentially stacked between the light emitting cells, and a transparent electrode covering the upper surface of the light emitting cells.

Abstract: An electrostatic micro switch includes a fixed electrode disposed on a fixed substrate; a movable substrate elastically supported by the fixed substrate, the movable substrate including a movable electrode facing the fixed electrode. The movable substrate includes a semiconductor including a plurality of regions having different values of resistivity and a region of high resistivity is disposed near the movable electrode.

Abstract: A light-emitting device that improves the injection efficiency of electrons or holes by providing electrons or holes to an emitting layer using nano size needles, including a first electrode with a first polarity a second electrode with a second polarity opposite to the first polarity an emitting layer interposed between the first electrode and the second electrode to emit light and a plurality of conductive needles inserted in the first electrode and extending toward the emitting layer.

Abstract: A thin film transistor and a method of fabricating the same capable of reducing stress of a substrate caused by a metal layer of the drain and source electrodes, the thin film transistor including a substrate; a semiconductor layer disposed on the substrate and including source, drain and channel regions; a gate insulating layer disposed on the substrate including the semiconductor layer; a gate electrode disposed on the gate insulating layer to correspond to the channel region of the semiconductor layer; an interlayer insulating layer disposed on the substrate including the gate electrode, and having contact holes connected with the source and drain regions of the semiconductor layer; and source and drain electrodes connected with the source and drain regions through the contact holes, wherein the source and drain electrodes include a first metal layer, a second metal layer, and a metal oxide layer interposed between the first metal layer and the second metal layer.