Patents Examined by Joseph Nguyen
  • Patent number: 7633124
    Abstract: A silicon nitride film having a thickness of 3 nm or less is formed on the surfaces of a P-well and N-well, as well as on the upper and side surfaces of a gate electrode, in which the silicon nitride film can be formed, for example, by exposing the surface of the P-well and N-well, and the upper and side surfaces of the gate electrode to a nitrogen-gas-containing plasma using a magnetron RIE apparatus. Then, pocket layers, extension layers and source/drain layers are formed while leaving the silicon nitride film unremoved.
    Type: Grant
    Filed: July 14, 2006
    Date of Patent: December 15, 2009
    Assignee: Fujitsu Microelectronics Limited
    Inventor: Takashi Saiki
  • Patent number: 7629191
    Abstract: A semiconductor device can include a channel including a zinc-indium oxide film.
    Type: Grant
    Filed: September 26, 2006
    Date of Patent: December 8, 2009
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Hai Q. Chiang, Randy L. Hoffman, David Hong, Nicole L. Dehuff, John F. Wager
  • Patent number: 7626269
    Abstract: The invention includes semiconductor assemblies having two or more dies. An exemplary assembly has circuitry associated with a first die front side electrically connected to circuitry associated with a second die front side. The front side of the second die is adjacent a back side of the first die, and a through wafer interconnect extends through the first die. The through wafer interconnect includes a conductive liner within a via extending through the first die. The conductive liner narrows the via, and the narrowed via is filled with insulative material. The invention also includes methods of forming semiconductor assemblies having two or more dies; and includes electronic systems containing assemblies with two or more dies.
    Type: Grant
    Filed: July 6, 2006
    Date of Patent: December 1, 2009
    Assignee: Micron Technology, Inc.
    Inventors: Steve Oliver, Warren M. Farnworth
  • Patent number: 7626201
    Abstract: A semiconductor device can include a channel including a zinc-indium oxide film.
    Type: Grant
    Filed: October 4, 2006
    Date of Patent: December 1, 2009
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Hai Q. Chiang, Randy L. Hoffman, David Hong, Nicole L. Dehuff, John F. Wager
  • Patent number: 7622200
    Abstract: The present invention relates to a thin film light emitting element which has low drive voltage. In particular, the present invention relates to a thin film light emitting element which has low drive voltage and in which color purity and luminous efficiency are not deteriorated. A structure of a light emitting element of the present invention comprises at least an electron transporting layer, a light emitting layer containing a luminescent substance, a first region, and a second region are provided between electrodes, wherein the electron transporting layer includes the second region between the light emitting layer and the first region, the first region includes a substance containing a polycyclic condensed ring, and the second region does not include the substance containing a polycyclic condensed ring.
    Type: Grant
    Filed: May 18, 2005
    Date of Patent: November 24, 2009
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Nobuharu Ohsawa, Hiroko Abe
  • Patent number: 7615785
    Abstract: The invention provides a light emitting device which is capable of displaying on both sides, has a small volume, and is capable of being used as a module. A light emitting element represented by an EL element and the like is used in a pixel portion, and two pixel portions are provided in one light emitting device. A first pixel portion has a structure to emit light only from a counter electrode side of the light emitting element. A second pixel portion has a structure to emit light only from a pixel electrode side of the light emitting element. That is, in the first pixel portion and the second pixel portion, directions of light emission are reverse in front and back.
    Type: Grant
    Filed: August 30, 2007
    Date of Patent: November 10, 2009
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yu Yamazaki, Aya Anzai, Tomoyuki Iwabuchi
  • Patent number: 7608862
    Abstract: A light emitting device comprises at least two lead wires, a light emitting element that is disposed on an end portion of at least one of said lead wires and connected electrically with the end portion and the other lead wire, and a phosphor that absorbs at least part of the light emitted from said light emitting element and emanates light having different wavelengths from the wavelength of the light emitted from said light emitting element, wherein the excitation spectrum of said phosphor has a flat region in a wavelength range including a primary wavelength of the light from said light emitting element.
    Type: Grant
    Filed: March 1, 2005
    Date of Patent: October 27, 2009
    Assignees: Fujikura Ltd., National Institute for Materials Science
    Inventors: Ken Sakuma, Koji Omichi, Naoto Hirosaki
  • Patent number: 7608881
    Abstract: A thin-film device comprises: a substrate; a flattening film made of an insulating material and disposed on the substrate; and a capacitor provided on the flattening film. The capacitor incorporates: a lower conductor layer disposed on the flattening film; a dielectric film disposed on the lower conductor layer; and an upper conductor layer disposed on the dielectric film. The thickness of the dielectric film falls within a range of 0.02 to 1 ?m inclusive and is smaller than the thickness of the lower conductor layer. The surface roughness in maximum height of the top surface of the flattening film is smaller than that of the top surface of the substrate and equal to or smaller than the thickness of the dielectric film. The surface roughness in maximum height of the top surface of the lower conductor layer is equal to or smaller than the thickness of the dielectric film.
    Type: Grant
    Filed: October 27, 2006
    Date of Patent: October 27, 2009
    Assignee: TDK Corporation
    Inventors: Hajime Kuwajima, Masahiro Miyazaki, Akira Furuya
  • Patent number: 7595520
    Abstract: An MTJ in an MRAM array or TMR read head is disclosed in which a low magnetization capping layer is a composite having a NiFeHf inner layer formed on a NiFe or CoFeB/NiFe free layer, a Ta middle layer, and a Ru outer layer on the Ta layer. For example, a low magnetization NiFeHf layer is achieved by co-sputtering NiFe and Hf targets with a forward power of 400 W and 200 W, respectively. A higher Hf content increases the oxygen gettering power of the NiFeHf layer and the thickness is modified to change dR/R, RA, and magnetostriction values. A so-called dead layer between the free layer and capping layer is restored by incorporating a NiFeHf layer on the free layer to improve lattice matching. The Fe content in the NiFe target used to make the NiFeHf layer is preferably the same as in the NiFe free layer.
    Type: Grant
    Filed: July 31, 2006
    Date of Patent: September 29, 2009
    Assignee: MagIC Technologies, Inc.
    Inventors: Cheng T. Horng, Ru-Ying Tong
  • Patent number: 7595540
    Abstract: A semiconductor device including a package (2) having a plurality of wall portions (9a) and a plurality of conductor portions (4), a semiconductor element such as a solid-state image pickup device (1) mounted in an internal space of the base, thin metal wires (5) electrically connecting the semiconductor element and the conductor portions (4) between the wall portions (9a), a resin sealing material (7) implanted in the spaces between the wall portions (9a), and a closing member such as a cover glass (6). The region for connecting the thin metal wires (5) and the wall portion (9a) region overlap each other, so that the device can be reduced in size and in height. The cover glass (6) can not move easily from the correct position because the wall portions (9a) serve as supporting columns, thereby improving the yield.
    Type: Grant
    Filed: July 18, 2006
    Date of Patent: September 29, 2009
    Assignee: Panasonic Corporation
    Inventors: Toshiyuki Fukuda, Eizou Fujii, Yutaka Fukai, Yutaka Harada, Kiyokazu Itoi
  • Patent number: 7592633
    Abstract: A semiconductor lamination portion is formed on a substrate by laminating semiconductor layers so as to form a light emitting layer, and a plurality of light emitting units are formed by separating the semiconductor lamination portion electrically into a plurality of units. Each of the units has a pair of electric connecting portions which are connected to a pair of conductivity type layers and they are connected to each other with a wiring film. Each of the plurality of the light emitting units is separated electrically by dividing the conductivity type layers of the semiconductor lamination portion with at least twofold separating grooves (a first separating groove and a second separating groove). As a consequence, a semiconductor light emitting device with a high luminance and being formed in a monolithic type having a plurality of light emitting units can be obtained to solve a problem of a short-circuit occurrence between the light emitting units while keeping high reliability of wiring or the like.
    Type: Grant
    Filed: May 16, 2006
    Date of Patent: September 22, 2009
    Assignee: Rohm Co., Ltd.
    Inventor: Yukio Shakuda
  • Patent number: 7589355
    Abstract: A light emitting diode is provided. The light emitting diode includes a semiconductor layer that forms a light emitting diode structure and has a major face and an end face inclined at an angle ?1 to the major face, and a reflector that is provided outside the end face with being opposed to the end face, and includes at least a portion inclined at an angle ?2 to the major face, the angle ?2 being smaller than the angle ?1.
    Type: Grant
    Filed: June 6, 2006
    Date of Patent: September 15, 2009
    Assignee: Sony Corporation
    Inventors: Katsuhiro Tomoda, Jun Suzuki, Masato Doi, Kensuke Kojima
  • Patent number: 7582972
    Abstract: A semiconductor device includes a semiconductor substrate with circuit elements and electrode pads formed on one surface. This surface is covered by a dielectric layer with openings above the electrode pads. A metal layer is deposited on the dielectric layer and patterned to form a conductive pattern with traces leading to the electrode pads. A protective layer having openings exposing part of the conductive pattern is formed. Each opening is covered by an electrode such as a solder bump, which is electrically connected through the conductive pattern to one of the electrode pads. This structure enables the thickness of the protective layer, which may function as a package of the semiconductor device, to be reduced. The protective layer may be formed from a photosensitive material, simplifying the formation of the openings for the electrodes.
    Type: Grant
    Filed: December 6, 2005
    Date of Patent: September 1, 2009
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Kiyonori Watanabe
  • Patent number: 7579688
    Abstract: The invention of the present application provides a heat radiation structure of a semiconductor device, and includes a substrate having, on a surface thereof, a first area on which the semiconductor device is mounted, and a second area which surrounds the first area. The semiconductor device has a first surface and a second surface opposite to the first surfaces, and is formed with a plurality of terminals provided on the first surface. The semiconductor device is mounted on the substrate in such a manner that the first surface is opposite to the surface of the substrate. A first heat radiating film is formed on the second area of the substrate, and a second heat radiating film is formed on the second surface of the semiconductor device, with the second heat radiating film being spaced apart from the first heat radiating film.
    Type: Grant
    Filed: April 13, 2004
    Date of Patent: August 25, 2009
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Takashi Noguchi
  • Patent number: 7560748
    Abstract: A light emitting diode unit including a base (100) made of anodized aluminum and a printed board (101) attached to the base (100) and the printed board (101) including a predetermined conductive pattern (102) and an opening (101a) having an area for die-bonding at least one LED chip (113) to the base (100) through a transparent paste, an upper electrode of the at least one LED chip being wire-bonded to a conductive pattern (102) provided on the printed board (101) through a gold line (110), and a lens member (105) including at least two sealing resin-injection holes (106c) and being attached to the printed board (101) to form a space surrounding the at least one LED chip on the base, and the space being filled with the sealing resin by way of the resin-injection holes (106c) to seal the at least one LED chip.
    Type: Grant
    Filed: October 30, 2006
    Date of Patent: July 14, 2009
    Assignee: Citizen Electronics Co., Ltd.
    Inventors: Mitsunori Ishizaka, Koichi Fukasawa, Sadato Imai
  • Patent number: 7554129
    Abstract: A light emitting device can include a substrate, electrodes provided on the substrate, a light emitting diode configured to emit light, the light emitting diode being provided on one of the electrodes, phosphors configured to change a wavelength of the light, and an electrically conductive device configured to connect the light emitting diode with another of the plurality of electrodes. The phosphors can substantially cove at least a portion of the light emitting diode. The phosphor may include aluminate type compounds, lead and/or copper doped silicates, lead and/or copper doped antimonates, lead and/or copper doped germanates, lead and/or copper doped germanate-silicates, lead and/or copper doped phosphates, or any combination thereof.
    Type: Grant
    Filed: December 30, 2004
    Date of Patent: June 30, 2009
    Assignee: Seoul Semiconductor Co., Ltd.
    Inventors: Gundula Roth, Walter Tews, Chung Hoon Lee
  • Patent number: 7547918
    Abstract: An auxiliary line including a guide layer and an auxiliary metallic member is formed with respect to a signal transmitting line or a main auxiliary capacitance line formed on a glass substrate. The guide layer is formed in the same layer where pixel electrodes are formed. The auxiliary metallic member is formed by using a method such as an inkjet method, in which fine particles of metal is ejected or dropped.
    Type: Grant
    Filed: June 22, 2005
    Date of Patent: June 16, 2009
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Kyoko Azumada, Kenji Nakamura, Atsushi Ban, Tatsuya Fujita
  • Patent number: 7541123
    Abstract: An imaging member includes an electrically conductive layer; a positive charge blocking layer, an imaging layer, and an undercoat layer. The undercoat layer is intermediate the imaging layer and the electrically conductive layer. The undercoat layer includes a film forming polymer and a particulate material dispersed therein. The particulate material supports a charge blocking material thereon.
    Type: Grant
    Filed: June 20, 2005
    Date of Patent: June 2, 2009
    Assignee: Xerox Corporation
    Inventors: Satchidanand Mishra, Robert C. U. Yu, Kathleen M. Carmichael
  • Patent number: 7531843
    Abstract: A structure of light-emitting diode (LED) dies having an AC loop (a structure of AC LED dies), which is formed with at least one unit of AC LED micro-dies disposed on a chip. The unit of AC LED micro-dies comprises two LED micro-dies arranged in mutually reverse orientations and connected with each other in parallel, to which an AC power supply may be applied so that the LED unit may continuously emit light in response to a positive-half wave voltage and a negative-half wave voltage in the AC power supply. Since each AC LED micro-die is operated forwardly, the structure of AC LED dies also provides protection from electrical static charge (ESD) and may operate under a high voltage.
    Type: Grant
    Filed: November 23, 2004
    Date of Patent: May 12, 2009
    Assignee: Industrial Technology Research Institute
    Inventors: Ming-Te Lin, Fei-Chang Hwang, Chia-Tai Kuo
  • Patent number: 7524698
    Abstract: A method and apparatus for handling and positioning half plated balls for socket application in ball grid array packages. The half plated balls, comprising a first side adapted to be soldered and a second side adapted to establish reliable solderless electrical contact, are embedded in a soft foil, with a common orientation. The soft foil is positioned on a clam-receiving tool and a vacuumed caved cover clam is fitted on the balls and then pushed to cut and separate the polymer sheet from the copper ball surface. The vacuumed caved cover clam is then lifted with the oriented copper balls entrapped inside and the vacuumed caved cover clam places the entrapped balls on the laminate pads, with a deposit of low melt alloy. The air vacuum is deactivated and the cover is lifted, leaving the balls positioned on the pads while the soldering process is initiated and solder joints are formed to fix the balls.
    Type: Grant
    Filed: December 2, 2005
    Date of Patent: April 28, 2009
    Assignee: International Business Machines Corporation
    Inventors: Giorgio Viero, Stefano Sergio Oggioni, Michele Castriotta