Abstract: An automotive control system includes a safety processor and a system-on-a-chip. The SoC includes a primary processor, a safety monitor, first and second GPIO banks, and a debug interface. The safety monitor is configured to detect a fault condition of the primary processor and to provide an indication of the fault condition to the safety processor. The first GPIO bank is coupled to the primary processor to provide input/output operations to a non-critical function of an automobile, while the second GPIO bank is coupled for a critical function of the automobile. The debug interface is coupled to the second GPIO bank to form a scan chain with input and output registers of the second GPIO bank, and is coupled to the safety processor to receive control information for the scan chain to provide input/output operations to the critical function of the automobile when the safety monitor provides the indication.

Abstract: Methods, systems and computer program products for automated test case generation are provided herein. A computer-implemented method includes selecting sample input data as a test case for a system under test, executing the test case on the system under test to obtain a result, and applying the result to a local explainer function to obtain at least a portion of a corresponding decision tree. The method further includes determining at least one path constraint from the decision tree, solving the path constraint to obtain a solution, and generating at least one other test case for the system under test based at least in part on the solution of the path constraint. The steps of the method are illustratively repeated in each of one or more additional iterations until at least one designated stopping criterion is met. The resulting test cases form a test suite for testing of a deep neural network (DNN) or other system.

Abstract: Apparatuses of systems that provide Safety Integration Levels (SILs) and Hardware Fault Tolerance (HFT) include a first die, the first die including first processing logic connected to a first connection and the first connection connected to second processing logic of a second die. The first die may further include a second connection to an input/output (I/O) channel where the second connection is coupled to the first processing logic. The apparatuses may further include a second die, the second die including second processing logic and a third connection from a secondary device coupled to the second processing logic. The secondary device is outside the system. The second processing logic is configured to select among three configurations based on signals from the second processing logic and the secondary device: sending first output data on the I/O output channel, sending second output data on the I/O output channel, or de-energizing the I/O channel.

Abstract: An electronic control device includes a rewritable configuration memory composed of a plurality of frames in which logic circuit information is stored, a reconfiguration control unit configured to rewrite the logic circuit information of the frames, a logic unit configured to form a logic circuit based on the logic circuit information stored in the frames, and a configuration memory diagnosis unit configured to read the logical circuit information stored in the frames of the configuration memory and to perform error detection which is detection of an error in the stored logic circuit information, in which when the frames are rewritten by the reconfiguration control unit, the configuration memory diagnosis unit performs the error detection of ones of the frames that are rewritten prior to ones of the frames that are not rewritten.

Abstract: Apparatus and methods for controlling unmanned systems (UMSs), such as unmanned aircraft, are provided. A UMS can be provided that includes a network, auxiliary systems, and a payload, where the network can connect the auxiliary systems and the payload. A network switch of the network can logically separate the network into at least a second tier of communications and a third tier of communications. The network can be used to control the UMS by at least: controlling the auxiliary systems using messages communicated by the second tier of communications, and communicating with the payload using messages communicated by the third tier of communications.

Abstract: A system includes a host and a display. The host includes a programmable logic device (PIP), a baseboard management controller (BMC) and a switch. The PLD performs a power-on procedure based on a power-on sequence code, generates variable character information in the power-on procedure, and fills the variable character information into a variable field in a preset log text file to result in an updated log text file. When it is determined that the power-on procedure is not normally completed, the PLD controls the switch to switch to a debug mode, and transmits a video signal containing debug information corresponding to the updated log text file to the switch so that the video signal is outputted to the display.

Abstract: An information handling system may include a central processing unit (CPU), a graphics processing unit (GPU) including a plurality of processing cores, a memory coupled to the CPU and to the GPU, and a basic input/output system (BIOS). While the information handling system is in a pre-boot environment and prior to initialization of an operating system of the information handling system, the BIOS may cause the central processing unit to select respective portions of the memory for failure testing; and cause individual ones of the plurality of processing cores of the GPU to carry out the failure testing of the respective portions of the memory.

Abstract: An arrangement for redundant data processing has an integrated circuit in which the functionality of a multi-core processor is implemented. Processor cores (40; 50) of the multi-core processor are each designed to execute a useful program. The results which emerge from the execution of the useful program by the different processor cores are compared by a comparison module of the arrangement. The processor cores differ from one another with respect to an address or data structure (AS1, AS2; DS1, DS2) which is used by a processor core to respectively store and read data in or from a memory area (70; 80) that is assigned to the particular processor core. In terms of hardware, the individual processor cores are at least partially implemented separately in the integrated circuit.

Abstract: A semiconductor device of an embodiment includes a main circuit configured to perform a predetermined operation to an input signal to output an output signal, an inverse operation circuit configured to receive the output signal of the main circuit as an input, and perform an inverse operation of the predetermined operation by using the output signal to output an inverse operation result signal, and a comparison circuit configured to compare the input signal and the inverse operation result signal, and output a predetermined signal when the input signal and the inverse operation result signal do not coincide with each other.

Abstract: The memory error determination device includes a processor configured to: detect a memory element in which an error has occurred in each of a plurality of layers included in a memory being three-dimensionally stacked, specify a position of each memory element in which the error has occurred in each of the plurality of layers, and determine that, when the position of each memory element in which the error has occurred is linearly aligned across a predetermined number of layers among the plurality of layers, the predetermined number being two or more, an error that has occurred in the memory is a soft error due to radiation incident on the memory.

Abstract: Systems and methods for intelligent fan identification are described. In some embodiments, an Information Handling System (IHS) may include: an embedded controller (EC); and a memory coupled to the EC, the memory having program instructions stored thereon that, upon execution by the EC, cause the IHS to: detect a cooling fan configuration issue; determine that a number of cooling fans in the IHS has not changed between a previous configuration and a current configuration; and in response to the determination, abstain from identifying the cooling fan configuration issue as a cooling fan error.

Abstract: A non-transitory computer-readable storage medium storing a program that causes a computer to execute a process, the process includes determining whether an error log is included in an operation log over a terminal; when the error log is included in the operation log, specifying a start timing and a stop timing of a script including the error log stored in a memory based on the operation log; and extracting moving image data output to the terminal during execution of the script based on time information related to the specified start timing and stop timing of the script.

Abstract: It is detected whether write data has been correctly transmitted to a storage device under a protocol for directly connecting the storage device to a processor. An information processing system including: a processor; a memory; and a storage device, the processor first transmitting to the storage device, a command to invalidate data in a data area and which is designated by a write command, the storage device invalidating the data, the processor second transmitting to the storage device, the write command to write the data into the data area, and the storage device writing the data into the data area in accordance with the write command, validating the data in a data area into which the storage device has been successful in writing the data, and maintaining the data invalidated in a data area into which the storage device has failed in writing the data.

Abstract: Aspects of the present invention disclose a method for a two-node storage system. The method includes one or more processors creating a plurality of first logic unit groups in a first storage node of a storage system. The method further includes mapping each of the plurality of first logic unit groups to a number of storage slices from different storage devices in the first storage node. The method further creating a plurality of second logic unit groups in a second storage node of the storage system, by mirroring storage slices from a storage device in the first storage node to multiple storage devices in the second storage node. In response to identifying a failure of a first storage device in the first storage node, the method further includes recovering lost data based on data in the second storage node.

Abstract: In one set of embodiments, a storage system can execute a repair process for a first component of a file or object stored on the storage system, where the repair process is initiated in response to the first component becoming inaccessible by the storage system, and where the file or object is split across a plurality of components including the first component. The executing can include, for each chunk in an address space of the first component starting from an initial chunk pointed to by a cursor: (1) determining whether the chunk is mapped to the first component, (2) if the chunk is mapped to the first component, copying data for the chunk from a mirror copy of the first component to a second component in the plurality of components, and (3) updating the cursor to point to a next chunk in the address space.

Abstract: Techniques are disclosed relating to testing application code. A computer system, in various embodiments, receives application code to be tested by the computer system and separate information defining actions to be performed at specified locations within the application code. In various embodiments, the computer system executes the application code in a test environment in which the actions defined by the separate information are retrieved and performed by a plurality of threads of the application code at the specified locations to control flow of the plurality of threads through the application code. In some embodiments, a first one of the plurality of threads is operable to perform at least one of the actions to control the flow of a second one of the plurality of threads.

Abstract: Various systems and methods for implementing automatic model generation for performance monitoring are described herein. A performance monitoring system includes a model manager to: identify a performance model that predicts performance of an operational node, the performance model based on telemetry data from the operational node; and implement an automatic verification operation to analyze the performance model and revise the performance model when the performance model is no longer valid; and an event processor to: initiate a remedial action at the operational node when the performance model indicates an alert state.

Abstract: An indication that a selected data set stored on a selected tape storage media is associated with a failure is received. An error correction data set group for the selected data set is identified, and wherein the error correction data set group includes a plurality of data sets and each data set included in the error correction data set group is stored on a different tape storage media. One or more data sets other than the selected data set that are included in the error correction data set group are selectively obtained from one or more corresponding tape storage media other than the selected tap storage media without reading entire contents of the one or more corresponding tape storage media. The obtained one or more data sets are utilized to recover at least a portion of the selected data set associated with the failure.

Abstract: Techniques disclosed herein relate generally to debugging complex computing systems, such as those executing neural networks. A neural network processor includes a processing engine configured to execute instructions to implement multiple layers of a neural network. The neural network processor includes a debugging circuit configured to generate error detection codes for input data to the processing engine or error detection codes for output data generated by the processing engine. The neural network processor also includes an interface to a memory device, where the interface is configured to save the error detection codes generated by the debugging circuit into the memory device. The error detection codes generated by the debugging circuit are compared with expected error detection codes generated using a function model of the neural network to identify defects of the neural network.

Abstract: Provided are a computer program product, system, and method for using a machine learning module to determine when to perform error checking of a storage unit. Input on attributes of at least one storage device comprising the storage unit are provided to a machine learning module to produce an output value. An error check frequency is determined from the output value. A determination is made as to whether the error check frequency indicates to perform an error checking operation with respect to the storage unit. The error checking operation is performed in response to determining that the error checking frequency indicates to perform the error checking operation.