Patents Examined by Joseph Schoenholtz
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Patent number: 10177251Abstract: A semiconductor device according to an embodiment includes a silicon carbide layer having a first plane and a second plane; a source electrode; a drain electrode; first and second gate electrodes located; an n-type drift region and a p-type body region; n-type first and second source regions; a p-type first silicon carbide region and p-type second silicon carbide region having a p-type impurity concentration higher than the body region; first and second gate insulating layers; a p-type third silicon carbide region contacting the first silicon carbide region, a first n-type portion being located between the first gate insulating layer and the third silicon carbide region; and a p-type fourth silicon carbide region contacting the second silicon carbide region, a second n-type portion being located between the second gate insulating layer and the fourth silicon carbide region.Type: GrantFiled: February 8, 2018Date of Patent: January 8, 2019Assignee: Kabushiki Kaisha ToshibaInventors: Tatsuo Shimizu, Takashi Shinohe, Ryosuke Iijima
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Patent number: 10170224Abstract: A structure and method for fabricating a laterally configured thin film varistor surge protection device using low temperature sputtering techniques which do not damage IC device components contiguous to the varistor being fabricated. The lateral thin film varistor may include a continuous layer of alternating regions of a first metal oxide layer and a second metal oxide layer formed between two laterally spaced electrodes using a low temperature sputtering process followed by a low temperature annealing process.Type: GrantFiled: November 22, 2017Date of Patent: January 1, 2019Assignee: International Business Machines CorporationInventors: Jeffrey P. Gambino, Richard S. Graf, Sudeep Mandal
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Patent number: 10164211Abstract: According to the present disclosure, an organic light emitting material and a metal may be entirely deposited on a substrate without using an open mask to form an organic light emitting device, thereby facilitating application to a roll fabrication apparatus. A side surface of an organic light emitting layer may be exposed to the outside, but a step structure may be formed on an outer portion of the substrate, and the organic light emitting layer is disconnected between an outer region and a lighting region by the step of the step structure, thereby preventing moisture that penetrates into the organic light emitting layer in the outer region from being propagated to the organic light emitting layer in the lighting region.Type: GrantFiled: September 13, 2017Date of Patent: December 25, 2018Assignee: LG Display Co., Ltd.Inventors: Namkook Kim, Soonsung Yoo, Taejoon Song, Jungeun Lee, Shinbok Lee, Kyungha Lee
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Patent number: 10164159Abstract: A light-emitting diode (LED) package includes: a reflective structure including a cavity, a bottom portion having a through hole, and a sidewall portion surrounding the cavity and the bottom portion and having an inclined inner side surface; an electrode pad inserted into the through hole; an LED on the bottom portion in the cavity, the LED including a light-emitting structure electrically connected to the electrode pad and a phosphor formed on the light-emitting structure; and a lens structure filling the cavity and formed on the reflective structure.Type: GrantFiled: September 13, 2017Date of Patent: December 25, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jin-sub Lee, Yong-il Kim, Han-kyu Seong, Young-jin Choi
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Patent number: 10164185Abstract: In some embodiments, the present disclosure relates to a method of operating an RRAM cell having a PMOS access transistor. The method may be performed by turning on a PMOS transistor having a drain terminal coupled to a lower electrode of an RRAM device. A first voltage is provided to a source terminal of the PMOS transistor, and a second voltage is provided to a bulk terminal of the PMOS transistor. The second voltage is larger than the first voltage. A third voltage is provided to an upper electrode of the RRAM device. The third voltage is larger than the first voltage.Type: GrantFiled: September 12, 2017Date of Patent: December 25, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Sheng-Hung Shih, Kuo-Chi Tu, Chih-Yang Chang, Hsia-Wei Chen, Chin-Chieh Yang, Jen-Sheng Yang, Wen-Ting Chu, Yu-Wen Liao
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Patent number: 10157909Abstract: A 3D semiconductor device, the device including: a first layer including first transistors each including a silicon channel; a second layer including second transistors each including a silicon channel, the second layer overlaying the first transistors, where at least one of the second transistors is at least partially self-aligned to at least one of the first transistors; and a third layer including third transistors each including a single crystal silicon channel, the third layer underlying the first transistors, where a plurality of the third transistors form a logic circuit, and where the logic circuit is aligned to the second transistors with less than 200 nm alignment error, where the first layer thickness is less than one micron, and where the first transistor is a junction-less transistor.Type: GrantFiled: January 4, 2018Date of Patent: December 18, 2018Assignee: Monolithic 3D Inc.Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist
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Patent number: 10156599Abstract: Some embodiments include an apparatus for determining statistics of the current in various wiring systems exposed to diffuse electromagnetic fields. Other embodiments of related apparatuses and methods are also disclosed.Type: GrantFiled: December 16, 2015Date of Patent: December 18, 2018Assignees: Dassault Systemes Simulia Corp.Inventors: Robin Stewart Langley, Andrea Barbarulo, Louis Kovalevsky
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Patent number: 10153461Abstract: A display panel includes a display device, a first anti-reflection layer and a cover layer. The first anti-reflection layer is disposed over the display device, wherein the first anti-reflection layer comprises a first structural layer including a plurality of first protrusion structures opposite to the display device. The cover layer is disposed over the first anti-reflection layer.Type: GrantFiled: September 13, 2017Date of Patent: December 11, 2018Assignee: INT TECH CO., LTD.Inventor: Yu-Chen Liu
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Patent number: 10151737Abstract: This disclosure relates to a system and method for applying a prediction of permeability of shale gas in porous media at different pressure conditions to a shale gas production. The method uses a molecular model that accounts for slippage and adsorption effects under the different pressure conditions including simulated gas flows in a large computational domain representing a sample of shale rock. This system and method provides a computationally efficient processing to determine permeability variations of shale gas with the different pressure conditions.Type: GrantFiled: January 7, 2016Date of Patent: December 11, 2018Assignee: KING FAHD UNIVERSITY OF PETROLEUM AND MINERALSInventors: Jun Li, Abdullah S. Sultan
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Patent number: 10153451Abstract: An organic light emitting device includes a first emitting part on an anode, the first emitting part including a first emission layer and a first hole transport layer a second emitting part on the first emitting part, the second emitting part including a second emission layer and a second hole transport layer; a third emitting part on the second emitting part including a third emission layer and a third hole transport layer; and a cathode on the third emitting part. The third emitting part further includes a fourth emission layer to emit light having a same color as the third emission layer and includes a dopant and a mixed host of at least two hosts, and a fourth hole transport layer provided on the third hole transport layer while in contact with the third emission layer, and has a hole mobility lower than that of the third hole transport layer.Type: GrantFiled: March 22, 2017Date of Patent: December 11, 2018Assignee: LG Display Co., Ltd.Inventors: Taeshick Kim, Younseok Kam, Ki-Woog Song
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Patent number: 10153449Abstract: A novel light-emitting element or a highly reliable light-emitting element is provided. The light-emitting element includes an anode, a cathode, and an EL layer between the anode and the cathode. The EL layer includes at least a light-emitting layer. The light-emitting layer includes at least a first organic compound and a second organic compound. The energy for liberating halogen from a halogen-substituted product of the first organic compound in a radical anion state and in a triplet excited state is less than or equal to 1.00 eV. The amount of halogen-substituted product in the second organic compound is not increased with an increase in driving time of the light-emitting element.Type: GrantFiled: October 14, 2015Date of Patent: December 11, 2018Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Satoshi Seo, Takeyoshi Watabe, Rina Nakamura, Harue Osaka, Ayumi Sato, Kunihiko Suzuki, Hayato Yamawaki
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Patent number: 10147897Abstract: A synaptic transistor based on a metal nano-sheet and a method thereof are provided. A self-assembled floating gate layer is formed. The floating gate layer prevents leakage of electric charges transmitted from a channel layer, and also temporarily stores the transmitted electric charge. Thus, the synaptic transistor may be used as an effective memory for storing.Type: GrantFiled: September 13, 2017Date of Patent: December 4, 2018Assignee: GWANGJU INSTITUTE OF SCIENCE AND TECHNOLOGYInventors: Myung Han Yoon, Chang Hyun Kim
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Patent number: 10147899Abstract: Provided is a tandem organic electroluminescent element, comprising a first electrode, a first light emitting unit, a third electron transporting layer, a second electron transporting layer, a first electron transporting layer, a charge generation layer, a second light emitting unit and a second electrode which are stacked up from bottom to top; both the first electron transporting layer and the second electron transporting layer comprising n type dopant, and a concentration of the n type dopant in the first electron transporting layer being larger than a concentration of the n type dopant in the second electron transporting layer, and the third electron transporting layer comprising no n type dopant; the arrangement of the first, the second and the third electron transporting layers can reduce the energy barrier of injecting electrons into the first light emitting unit by the charge generation layer to make the electrons easy to be injected.Type: GrantFiled: February 15, 2017Date of Patent: December 4, 2018Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.Inventors: Aiguo Tu, Wei Yuan
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Patent number: 10147648Abstract: A vertical FinFET structure includes a metal layer disposed between adjacent fins of a multi-fin device. The metal layer, which is in electrical contact with a self-aligned work function metal layer, is adapted to decrease the overall resistance of the gate contact for the device. A lower gate contact resistance can improve the reliability and performance of the device, particularly in radio frequency (RF) applications. The metal layer can also extend laterally to provide a contact region for a gate contact.Type: GrantFiled: December 4, 2017Date of Patent: December 4, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Hui Zang, Josef Watts
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Patent number: 10141226Abstract: A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.Type: GrantFiled: November 30, 2017Date of Patent: November 27, 2018Assignee: Intel CorporationInventors: Mark T. Bohr, Tahir Ghani, Nadia M. Rahhal-Orabi, Subhash M. Joshi, Joseph M. Steigerwald, Jason W. Klaus, Jack Hwang, Ryan Mackiewicz
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Patent number: 10141297Abstract: An integrated device that includes a substrate, a device level layer formed over the substrate, and interconnect portion over the device level layer. The device level layer includes a plurality of first device level cells, each first device level cell comprising a first configuration. The device level layer includes a plurality of second device level cells. At least one second device level cell includes a second configuration that is different than the first configuration. The plurality of second device level cells is located over at least one region of the integrated device comprising at least one hotspot.Type: GrantFiled: December 4, 2017Date of Patent: November 27, 2018Assignee: QUALCOMM IncorporatedInventors: Palkesh Jain, Mehdi Saeidi, Jon James Anderson, Chethan Swamynathan, Richard Wunderlich
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Patent number: 10128402Abstract: To provide a method of manufacturing a display device having an excellent impact resistance property with high yield, in particular, a method of manufacturing a display device having an optical film that is formed using a plastic substrate. The method of manufacturing a display device includes the steps of: laminating a metal film, an oxide film, and an optical filter on a first substrate; separating the optical filter from the first substrate; attaching the optical filter to a second substrate; forming a layer including a pixel on a third substrate; and attaching the layer including the pixel to the optical filter.Type: GrantFiled: May 25, 2017Date of Patent: November 13, 2018Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Akio Yamashita, Yumiko Fukumoto, Yuugo Goto
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Patent number: 10121877Abstract: A method for fabricating a semiconductor device includes forming a semiconductor fin over a substrate. A first doped region is formed on a first end of the semiconductor fin. A second doped region is formed on a second end of the semiconductor fin. An extended contact is formed on the second doped region. A portion of the extended contact extends past an end of the semiconductor fin in a direction orthogonal to a channel of the semiconductor fin. A contact extension is formed on the portion of the extended contact extending past the end of the semiconductor fin. A contact is formed on the first doped region.Type: GrantFiled: September 13, 2017Date of Patent: November 6, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Terence B. Hook, Joshua M. Rubin, Tenko Yamashita
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Patent number: 10121835Abstract: To provide a display device including a pixel electrode formed on an insulating surface; a bank covering an end portion of the pixel electrode and having an opening formed therein in which the upper surface of the pixel electrode is exposed; an organic layer containing a light emitting layer and formed covering the opening; and an opposed electrode formed on the organic layer and the bank. The bank has a first layer formed on an end portion of the pixel electrode and the insulating surface, and a second layer formed on the first layer. The refractive index of the material forming the first layer is less than the refractive index of the material forming the second layer.Type: GrantFiled: June 28, 2017Date of Patent: November 6, 2018Assignee: Japan Display Inc.Inventor: Shigeru Sakamoto
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Patent number: 10121838Abstract: The present disclosure relates to a display device including a light emitting element display. The present disclosure suggests a flat panel display comprising: a substrate; a driving element disposed on a first surface of the substrate; an organic light emitting diode disposed on a second surface of the substrate; a through-hole penetrating the substrate from the front surface to the rear surface; and a connecting electrode filling the through-hole for linking the driving element to the organic light emitting diode.Type: GrantFiled: September 12, 2017Date of Patent: November 6, 2018Assignee: LG Display Co., Ltd.Inventors: Jongsik Shim, Youngjun Choi, Younsub Kim